Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 106 page image

106 www.xilinx.com 7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016Chapter 3: TransmitterTo calculate accurately the receiver’s bit error rate (BER), an external jitter tolerance tester shouldbe used. For the test, the GTP transceiver should loop the received error status back through thetransmitter by setting RXPRBS_ERR_LOOPBACK to 1 (Figure 3-19). The same setting should beapplied to RXPRBSSEL and TXPRBSSEL.TX Polarity ControlFunctional DescriptionIf TXP and TXN differential traces are accidentally swapped on the PCB, the differential datatransmitted by the GTP transceiver TX is reversed. One solution is to invert the parallel data beforeserialization and transmission to offset the reversed polarity on the differential pair. The TX polaritycontrol can be accessed through the TXPOLARITY input from the fabric user interface. It is drivenHigh to invert the polarity of outgoing data.X-Ref Target - Figure 3-18Figure 3-18: Link Test Mode with a PRBS-7 Pattern001001001001TXPRBSSEL TX PatternGeneratorTX PatternGeneratorRX PatternCheckerRX PatternCheckerTXPRBSFORCEERRRXPRBSSELRXPRBS_ERR_LOOPBACK =0RXPRBSERRRX_PRBS_ERR_CNTRXPRBSSELRXPRBSERRRX_PRBS_ERR_CNTRXPRBS_ERR_LOOPBACK =0TXPRBSSELTXPRBSFORCEERRUG482_c3_17_110911X-Ref Target - Figure 3-19Figure 3-19: Jitter Tolerance Test Mode with a PRBS-7 PatternJitter Tester001001TXPRBS-7 patternwith jitterTX PatternGeneratorRXPatternCheckerRX PatternCheckerRXPRBSSELRXPRBSERRRX_PRBS_ERR_CNTRXPRBS_ERR_LOOPBACK =1TXPRBSSELTXPRBSFORCEERRUG482_c3_18_110911Send Feedback