126 www.xilinx.com 7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016Chapter 4: Receiver9. RX Byte and Word Alignment, page 16110. RX 8B/10B Decoder, page 17011. RX Buffer Bypass, page 17412. RX Elastic Buffer, page 18713. RX Clock Correction, page 19114. RX Channel Bonding, page 19815. RX Gearbox, page 20716. FPGA RX Interface, page 214RX Analog Front EndFunctional DescriptionThe RX analog front end (AFE) is a high-speed current-mode input differential buffer (seeFigure 4-1). It has these features:• Configurable RX termination voltage• Calibrated termination resistorsX-Ref Target - Figure 4-2Figure 4-2: RX Analog Front End+–+–FPGABoard ACJTAG RXACJTAG RX50Ω50Ω MGTAVTT ProgrammableGNDFLOATMGTAVTTMGTAVTT~100 nF~100 nFRX_CM_SEL[1:0]UG482_c4_02_110911RX_CM_TRIM[3:0]Send Feedback
