Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 197 page image

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 197UG482 (v1.9) December 19, 2016RX Channel BondingTo preserve comma alignment through the elastic buffer, CLK_COR_SEQ_LEN andALIGN_COMMA_WORD must be selected such that they comply with Table 4-38.Clock Correction OptionsCLK_COR_REPEAT_WAIT is used to control the clock correction frequency. This value is set tothe minimum number of RXUSRCLK cycles required between clock correction events. Thisattribute is set to 0 to allow clock correction to at occur any time. Some protocols allow clockcorrection to occur at any time, but require that if the clock correction circuit removes sequences, atleast one sequence stays in the stream. For protocols with this requirement,CLK_COR_KEEP_IDLE is set to TRUE.Monitoring Clock CorrectionThe clock correction circuit can be monitored using the RXCLKCORCNT and RXBUFSTATUSports. The RXCLKCORCNT entry in Table 4-36 shows how to decode the values ofRXCLKCORCNT to determine the status of the clock correction circuit. The RXBUFSTATUSentry in Table 4-36 shows how to decode the values of RXBUFSTATUS to determine how full theRX elastic buffer is.RX Channel BondingFunctional DescriptionProtocols such as XAUI and PCI Express combine multiple serial transceiver connections to createa single higher throughput channel. Each serial transceiver connection is called one lane. Unlesseach of the serial connections is exactly the same length, skew between the lanes can cause data tobe transmitted at the same time but arrive at different times. Channel bonding cancels out the skewbetween GTP transceiver lanes by using the RX elastic buffer as a variable latency block. Channelbonding is also called channel deskew or lane-to-lane deskew. GTP transceiver transmitters used fora bonded channel all transmit a channel bonding character (or a sequence of characters)simultaneously. When the sequence is received, the GTP transceiver receiver can determine theX-Ref Target - Figure 4-46Figure 4-46: Clock Correction Sequence MappingTable 4-38: Valid ALIGN_COMMA_WORD/CLK_COR_SEQ_LEN CombinationsALIGN_COMMA_WORD CLK_COR_SEQ_LEN1 1, 2, 42 2, 4UG482_c4_28_1110114CLK_COR_SEQ_x_4 CLK_COR_SEQ_x_3 CLK_COR_SEQ_x_2CLK_COR_SEQ_x_ENABLECLK_COR_SEQ_x_13 2 1Send Feedback