Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 123 page image

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 123UG482 (v1.9) December 19, 2016TX Out-of-Band SignalingNote: Figure 3-23 shows the sequence of events for the receiver present case and is not drawn toscale.Notes relevant to Figure 3-23:1. Ensure that the GTP transceiver has successfully entered the P1 power state with [TX/RX]PD= 2'd2 before receiver detection is performed by asserting TXDETECTRX.2. Wait for PHYSTATUS = 1'd1 to read RXSTATUS on the same PCLK cycle. In PCI Expressmode, PCLK is [TX/RX]USRCLK. If RXSTATUS = 3'd3, then the receiver is present. IfRXSTATUS = 3'd0, then the receiver is not present. Deassert TXDETECTRX to exit receiverdetection.TX Out-of-Band SignalingFunctional DescriptionEach GTP transceiver provides support for generating the out-of-band (OOB) sequences describedin the Serial ATA (SATA), Serial Attach SCSI (SAS) specification, and beaconing described in thePCI Express specification.Ports and AttributesTable 3-32 shows the OOB signaling related ports.X-Ref Target - Figure 3-23Figure 3-23: PCI Express Receiver DetectionCLK[TX/RX]PDTXDETECTRXPHYSTATUSRXSTATUS2’d23’d0 3’d3 3’d0UG482_c3_22_110911Table 3-32: TX OOB Signaling PortsPort Dir Clock Domain DescriptionTXCOMFINISH Out TXUSRCLK2 Indicates completion of transmission ofthe last SAS or SATA COM beacon.TXCOMINIT In TXUSRCLK2 Initiates transmission of the COMINITsequence for SATA/SAS.TXCOMSAS In TXUSRCLK2 Initiates transmission of the COMSASsequence for SAS.TXCOMWAKE In TXUSRCLK2 Initiates transmission of the COMWAKEsequence for SATA/SAS.Send Feedback