86 www.xilinx.com 7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016Chapter 3: TransmitterEnabling and Disabling 8B/10B EncodingTo enable the 8B/10B encoder, TX8B10BEN must be driven High. The TX 8B/10B encoder allowsbyte interleaved data to bypass the encoder on a per-byte basis. When TX8B10BEN is driven Low,all encoders are turned off and no data from TXDATA can be encoded. When TX8B10BEN is High,driving a bit from TX8B10BBYPASS High can make the corresponding byte channel fromTXDATA bypass 8B/10B encoding. When the encoder is turned off, the operation of the TXDATAport is as described in the FPGA TX interface.TX GearboxFunctional DescriptionSome high-speed data rate protocols use 64B/66B encoding to reduce the overhead of 8B/10Bencoding while retaining the benefits of an encoding scheme. The TX gearbox provides support for64B/66B and 64B/67B header and payload combining. The Interlaken interface protocolspecification uses the 64B/67B encoding scheme. Refer to the Interlaken specification for furtherinformation. The Interlaken specification can be downloaded from: http://www.interlakenalliance.com/.The TX gearbox supports 2-byte and 4-byte interfaces. Scrambling of the data is done in the FPGAlogic.Ports and AttributesTable 3-8 defines the TX gearbox ports.Table 3-8: TX Gearbox PortsPort Name Dir Clock Domain DescriptionTXGEARBOXREADY Out TXUSRCLK2 This output indicates if data can beapplied to the 64B/66B or 64B/67Bgearbox when GEARBOX_MODE isset to use the gearbox.0: No data can be applied1: Data must be appliedTXHEADER[2:0] In TXUSRCLK2 These ports are the header inputs. [1:0]are used for the 64B/66B gearbox, and[2:0] are used for the 64B/67B gearbox.TXSEQUENCE[6:0] In TXUSRCLK2 These inputs are used for the fabricsequence counter when the TX gearboxis used. [5:0] are used for the 64B/66Bgearbox, and [6:0] are used for the 64B/67B gearbox.TXSTARTSEQ In TXUSRCLK2 This input indicates the first word to beapplied after reset for the 64B/66B or64B/67B gearbox.Send Feedback