Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 206 page image

206 www.xilinx.com 7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016Chapter 4: Receiverone-half the minimum distance (in bytes or 10-bit codes) between channel bonding sequences. Thisminimum distance is determined by the protocol being used.Precedence between Channel Bonding and Clock CorrectionThe clock correction (see RX Clock Correction, page 191) and channel bonding circuits bothperform operations on the pointers of the RX elastic buffer. Normally, the two circuits work togetherwithout conflict, except when clock correction events and channel bonding events occursimultaneously. In this case, one of the two circuits must take precedence. To make clock correctiona higher priority than channel bonding, CLK_COR_PRECEDENCE must be set to TRUE. To makechannel bonding a higher priority, CLK_COR_PRECEDENCE must be set to FALSE.RX GearboxFunctional DescriptionThe RX gearbox provides support for 64B/66B and 64B/67B header and payload separation. Thegearbox uses output ports RXDATA[31:0] and RXHEADER[2:0] for the payload and header of thereceived data. Similar to TX Gearbox, page 86, the RX gearbox operates with the PMA using asingle clock. Because of this, occasionally, the output data is invalid. Output portsRXHEADERVALID and RXDATAVALID determine if the appropriate header and data are valid.The RX gearbox supports 2-byte and 4-byte interfaces.The data out of the RX gearbox is not necessarily aligned. Alignment is done in the FPGA logic. TheRXGEARBOXSLIP port can be used to slip the data from the gearbox cycle-by-cycle until correctalignment is reached. It takes a specific number of cycles before the bitslip operation is processedand the output data is stable. Descrambling of the data and block synchronization is done in theFPGA logic.Ports and AttributesTable 4-41 defines the RX gearbox ports.Table 4-41: RX Gearbox PortsPort Name Dir Clock Domain DescriptionRXDATAVALID[1:0] Out RXUSRCLK2 • Bit 0: Status output when Gearbox 64B/66B or 64B/67B is used, whichindicates that the data appearing on RXDATA is valid. For example,during 64B/66B encoding, this signal is deasserted every 32 cycles forthe 4-byte interface and every 64 cycles for the 2-byte interface.• Bit 1: Reserved.RXGEARBOXSLIP In RXUSRCLK2 When High, this port causes the gearbox contents to slip to the nextpossible alignment. This port is used to achieve alignment with the FPGAlogic. Asserting this port for one RXUSRCLK2 cycle changes the dataalignment coming out of the gearbox.RXGEARBOXSLIP must be deasserted for at least one cycle and thenreasserted to cause a new realignment of the data. If multiple realignmentsoccur in rapid succession, it is possible to pass the proper alignment pointwithout recognizing the correct alignment point in the FPGA logic.RXHEADER[2:0] Out RXUSRCLK2 Header outputs for 64B/66B (1:0) and 64B/67B (2:0).Send Feedback