Xilinx 7 Series User Manual
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7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 67UG482 (v1.9) December 19, 2016Dynamic Reconfiguration PortDynamic Reconfiguration PortFunctional DescriptionThe dynamic reconfiguration port (DRP) allows the dynamic change of parameters of theGTPE2_CHANNEL and GTPE2_COMMON primitives. The DRP interface is a processor-friendlysynchronous interface with an address bus (DRPADDR) and separated data buses for reading(DRPDO) and writing (DRPDI) configuration data to the primitives. An enable signal (DRPEN), aread/write signal (DRPWE), and a ready/valid signal (DRPRDY) are the control signals thatimplement read and write operations, indicate operation completion, or indicate the availability ofdata.Ports and AttributesTable 2-29 shows the DRP related ports for GTPE2_CHANNEL.Table 2-30 shows the DRP related ports for GTPE2_COMMON.Table 2-29: DRP Ports of GTPE2_CHANNELPort Dir Clock Domain DescriptionDRPADDR[8:0] In DRPCLK DRP address bus.DRPCLK In N/A DRP interface clock.DRPEN In DRPCLK DRP enable signal.0: No read or write operation performed.1: Enables a read or write operation.For write operations, DRPWE and DRPEN must bedriven High for one DRPCLK cycle only (seeFigure 2-23 for correct operation). For readoperations, DRPEN must be driven High for oneDRPCLK cycle only (see Figure 2-24 for correctoperation.DRPDI[15:0] In DRPCLK Data bus for writing configuration data from theFPGA logic resources to the transceiver.DRPRDY Out DRPCLK Indicates operation is complete for write operationsand data is valid for read operations. See Figure 2-23and Figure 2-24 for the assertion of DRPRDY signalafter a write and a read operation.DRPDO[15:0] Out DRPCLK Data bus for reading configuration data from theGTP transceiver to the FPGA logic resources.DRPWE In DRPCLK DRP write enable.0: Read operation when DRPEN is 1.1: Write operation when DRPEN is 1.For write operations, DRPWE and DRPEN should bedriven High for one DRPCLK cycle only. SeeFigure 2-23 for correct operation.Send Feedback |
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