RocketIO™ Transceiver User Guide www.xilinx.com 121UG024 (v2.3.2) June 24, 2004 1-800-255-7778MGT Package Pins RMGT Package PinsThe MGT is a hard core placed in the FPGA fabric; all package pins for the MGTs are dedicated onthe Virtex-II Pro device. This is shown in the package pin diagrams in the Virtex-II Pro PlatformFPGA User Guide. When creating a design, LOC constraints must be used to implement a specificMGT on the die. This LOC constraint also determines which package pins are used. Table 4-1 showsthe correlation between the LOC grid and the package pins themselves. The pin numbers areTXNPAD, TXPPAD, RXPPAD, and RXNPAD, respectively. The power pins are adjacent to thesepins in the package pin diagrams of the User Guide.Table 4-1: LOC Grid & Package Pins Correlation for FG256/456 & FF672LOCConstraintsFG256 FG456 FF6722VP2/2VP4 2VP2/2VP4 2VP7 2VP2/2VP4 2VP7GT_X0_Y0 T4, T5, T6, T7 AB7, AB8,AB9, AB10AB3, AB4,AB5, AB6AF18, AF17,AF16, AF15AF23, AF22,AF21, AF20GT_X0_Y1 A4, A5, A6, A7 A7, A8, A9,A10A3, A4, A5, A6 A18, A17, A16,A15A23, A22, A21,A20GT_X1_Y0 T10, T11, T12,T13AB13,AB14,AB15, AB16AB7, AB8,AB9, AB10AF12, AF11,AF10, AF9AF18, AF17,AF16, AF15GT_X1_Y1 A10, A11, A12,A13A13, A14, A15,A16A7, A8, A9,A10A12, A11, A10,A9A18, A17, A16,A15GT_X2_Y0 AB13, AB14,AB15, AB16AF12, AF11,AF10, AF9GT_X2_Y1 A13, A14, A15,A16A12, A11, A10,A9GT_X3_Y0 AB17, AB18,AB19, AB20AF7, AF6,AF5, AF4GT_X3_Y1 A17, A18, A19,A20A7, A6, A5, A4
