Xilinx RocketIO User Manual

Also see for RocketIO: User guide User guide User guide

Contents

Xilinx RocketIO User Manual Manual pdf 89 page image

RocketIO™ Transceiver User Guide www.xilinx.com 89UG024 (v2.3.2) June 24, 2004 1-800-255-7778Fabric Interface (Buffers) R• The RocketIO transceiver does not compute the 16-bit variant CRC used for Infiniband, andthus does not fulfill the Infiniband CRC requirement. Infiniband CRC can be computed in theFPGA fabric.• All CRC formats have minimum allowable packet sizes. These limits are larger than those setby the user mode, and are defined by the specific protocol.Fabric Interface (Buffers)Overview: Transmitter and Elastic (Receiver) BuffersBoth the transmitter and the receiver include buffers (FIFOs) in the data path. This section gives thereasons for including the buffers and outlines their operation.Transmitter Buffer (FIFO)The transmitter buffer’s write pointer (TXUSRCLK) is frequency-locked to its read pointer(REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of thetransmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK.Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-locked to the reference clock (REFCLK). Phase variations of up to one clock cycle are allowable. Asimple FIFO suffices for this purpose. A FIFO depth of four permits reliable operation with simpledetection of overflow or underflow, which might occur if the clocks are not frequency-locked.Overflow or underflow conditions are detected and signaled at the interface.Receiver BufferThe receiver buffer is required for two reasons:• To accommodate the slight difference in frequency between the recovered clock RXRECCLKand the internal FPGA core clock RXUSRCLK (clock correction)• To allow realignment of the input stream to ensure proper alignment of data being read throughmultiple transceivers (channel bonding)The receiver uses an elastic buffer, where “elastic” refers to the ability to modify the read pointer forclock correction and channel bonding.Ports and AttributesTXBUFERRWhen High, this port indicates that a transmit buffer underflow or overflow has occurred. Once setHigh, TXRESET must be asserted to clear this bit.TX_BUFFER_USEThis attribute allows the user to bypass the transmit buffer. A value of FALSE bypasses the buffer,while a TRUE keeps the buffer in the data path. This attribute should always be set to TRUE.RXBUFSTATUSThis 2-bit port indicates the status of the receiver elastic buffer. RXBUFSTATUS[1] High indicatesif an overflow/underflow error has occurred. (Once set High, the assertion of RXRESET or