Xilinx RocketIO User Manual

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Xilinx RocketIO User Manual Manual pdf 85 page image

RocketIO™ Transceiver User Guide www.xilinx.com 85UG024 (v2.3.2) June 24, 2004 1-800-255-7778CRC (Cyclic Redundancy Check) RPorts and AttributesTX_CRC_USE,RX_CRC_USEThese two attributes control whether the MGT CRC circuitry is enabled or bypassed. When set toTRUE, CRC is enabled. When set to FALSE, CRC is bypassed and must be implemented in theFPGA fabric.CRC_FORMATThere are four possible CRC modes: USER_MODE, FIBRE_CHAN, ETHERNET, andINFINIBAND. This attribute is modifiable only for the GT_XAUI and GT_CUSTOM primitives.Each mode has a Start of Packet (SOP) and End of Packet (EOP) setting to determine where to startand end the CRC monitoring. USER_MODE allows the user to define the SOP and EOP by settingthe CRC_START_OF_PKT and CRC_END_OF_PKT to one of the valid K-characters (Table B-2,page 141). The CRC is controlled by RX_CRC_USE and TX_CRC_USE. Whenever theseattributes are set to TRUE, CRC is used.The four modes are defined in the subsections following.USER_MODEUSER_MODE is the simplest CRC methodology. The CRC checks for the SOP and EOP, calculatesCRC on the data, and leaves the four remainders directly before the EOP. The CRC form for theuser-defined mode is shown in Figure 2-24, along with the timing for when RXCHECKINGCRCand RXCRCERR are asserted High with respect to the incoming data.To check the CRC error detection logic in a testing mode such as serial loopback, a CRC error canbe forced by setting TXFORCECRCERR to High, which incorporates an error into the transmitteddata. When that data is received, it appears “corrupted,” and the receiver signals an error byasserting RXCRCERR High at the same time RXCHECKINGCRC goes High. User logicdetermines the procedure that is invoked when a CRC error occurs.Note: Data length must be greater than 20 bytes for USER_MODE CRC generation. For CRCto operate correctly, at least four gap bytes are required between EOP of one packet and SOP ofthe next packet. The gap may contain clock correction sequences, provided that at least 4 bytesof gap remain after all clock corrections.FIBRE_CHANThe FIBRE_CHAN CRC is similar to USER_MODE CRC (Figure 2-24), with one exception: InFIBRE_CHAN, SOP and EOP are predefined protocol delimiters. Unlike USER_MODE,CRC Enabled 14 17 25 42 (2)Notes:1. See Table 2-6 and Table 2-7 for all MGT block latency parameters.2. This maximum may occur when certain conditions are present, and clock correction and channel bonding areenabled. If these functions are both disabled, the maximum will be near the typical values.3. To further reduce receive-side latency, refer to Appendix C, “Related Online Documents.”Table 2-20: Effects of CRC on Transceiver Latency(1)TXDATA to TXP and TXNin TXUSRCLK CyclesRXP and RXN to RXDATAin RXUSRCLK Cycles(3)Typical Maximum Typical Maximum