58 www.xilinx.com RocketIO™ Transceiver User Guide1-800-255-7778 UG024 (v2.3.2) June 24, 2004Chapter 2: Digital Design ConsiderationsRReset/Power DownThe receiver and transmitter have their own synchronous reset inputs. The transmitter reset recentersthe transmission FIFO, and resets all transmitter registers and the 8B/10B encoder. The receiverreset recenters the receiver elastic buffer, and resets all receiver registers and the 8B/10B decoder.Neither reset signal has any effect on the PLLs.After the DCM-locked signal is asserted, the resets can be asserted. The resets must be asserted fortwo USRCLK2 cycles to ensure correct initialization of the FIFOs. Although both the transmit andreceive resets can be attached to the same signal, separate signals are preferred. This allows theelastic buffer to be cleared in case of an over/underflow without affecting the ongoing TXtransmission. The following example is an implementation that resets all three data-widthtransceivers.Additional reset and power control descriptions are given in Table 2-8 and Table 2-9.TX FIFO 4 TXUSRCLK cycles (± 0.5)TX SERDES SERDES_10B = FALSE:1.5 TXUSRCLK cyclesSERDES_10B = TRUE:0.5 TXUSRCLK cycles (approx.)Table 2-6: Latency through Various Transmitter Components/Processes (Continued)Component/Process LatencyTable 2-7: Latency through Various Receiver Components/ProcessesComponent/Process LatencyRX SERDES 1.5 recovered clock (RXRECCLK) cyclesComma Detect/Realignment 2.5 or 3.5 recovered clock cycles(some bits bypass one register, depending on comma alignment)8B/10B Decoder included 1 recovered clock cyclebypassed 1 recovered clock cycleRX FIFO 18 RXUSRCLK cycles (± 0.5)RX GT/Fabric Interface1 Byte Data Path:2.5 RXUSRCLK2 cycles1.25 RXUSRCLK cycles2 Byte Data Path:1 RXUSRCLK2 cycle1 RXUSRCLK cycle4 Byte Data Path:1.25 RXUSRCLK2 cycles2.5 RXUSRCLK cyclesTable 2-8: Reset and Power Control DescriptionsPorts DescriptionRXRESET Synchronous receive system reset recenters the receiver elastic buffer, and resets the8B/10B decoder, comma detect, channel bonding, clock correction logic, and otherreceiver registers. The PLL is unaffected.TXRESET Synchronous transmit system reset recenters the transmission FIFO, and resets the8B/10B encoder and other transmission registers. The PLL is unaffected.POWERDOWN Shuts down the transceiver (both RX and TX sides).In POWERDOWN mode, transmit output pins TXP/TXN are not driven, but biased bythe state of transmit termination supply VTTX. If VTTX is not powered, TXP/TXNfloat to a high-impedance state. Receive input pins RXP/RXN respond similarly to thestate of receive termination supply VTRX.