RocketIO™ Transceiver User Guide www.xilinx.com 41UG024 (v2.3.2) June 24, 2004 1-800-255-7778Clocking RBREFCLKAt speeds of 2.5 Gb/s or greater, REFCLK configuration introduces more than the maximumallowable jitter to the RocketIO transceiver. For these higher speeds, BREFCLK configuration isrequired. The BREFCLK configuration uses dedicated routing resources that reduce jitter.BREFCLK must enter the FPGA through dedicated clock I/O. BREFCLK can connect to theBREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs. Ifall the transceivers on a Virtex-II Pro FPGA are to be used, two BREFCLKs must be created, one forthe top of the chip and one for the bottom. These dedicated clocks use the same clock inputs for allpackages:An attribute (REF_CLK_V_SEL) and a port (REFCLKSEL) determine which reference clock isused for the MGT PMA block. Figure 2-1 shows how REFCLK and BREFCLK are selected throughuse of REFCLKSEL and REF_CLK_V_SEL.Table 2-3 shows the BREFCLK pin numbers for all packages. Note that these pads must be used forBREFCLK operations.TopBREFCLK P GCLK4SBottomBREFCLK P GCLK6PN GCLK5P N GCLK7SBREFCLK2 P GCLK2S BREFCLK2 P GCLK0PN GCLK3P N GCLK1SFigure 2-1: REFCLK/BREFCLK Selection LogicTable 2-3: BREFCLK Pin NumbersPackageTop BottomBREFCLKPin NumberBREFCLK2Pin NumberBREFCLKPin NumberBREFCLK2Pin NumberFG256 A8/B8 B9/A9 R8/T8 T9/R9FG456 C11/D11 D12/C12 W11/Y11 Y12/W12FG676 B13/C13 C14/B14 AD13/AE13 AE14/AD14FF672 B14/C14 C13/B13 AD14/AE14 AE13/AD130001111.5V2.5VREF_CLK_V_SELREFCLKSEL refclk_outto PCS and PMArefclkrefclk2brefclkbrefclk2ug024_35_091802
