Xilinx RocketIO User Manual
Also see for RocketIO: User guideUser guideUser guide
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Contents
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RocketIO™ Transceiver User Guide www.xilinx.com 149UG024 (v2.3.2) June 24, 2004 1-800-255-7778Numerics8B/10B Encoding/Decodingbypassing 67decoder 61encoder 61overview 61ports and attributes 62serial output format 678B/10B Valid Characters 133AAC and DC Coupling 114Attributes & Ports (by function)8B/10B encoding/decoding 62buffers, fabric interface 89channel bonding 81clock correction 74CRC 85SERDES alignment 68synchronization logic 77Attributes (defined)ALIGN_COMMA_MSB 68CHAN_BOND__SEQ_LEN 81CHAN_BOND_LIMIT 82CHAN_BOND_MODE 81CHAN_BOND_OFFSET 82CHAN_BOND_ONE_SHOT 81CHAN_BOND_SEQ_*_* 81CHAN_BOND_SEQ_2_USE 81CHAN_BOND_WAIT 82CLK_COR_INSERT_IDLE_FLAG 75CLK_COR_KEEP_IDLE 75CLK_COR_REPEAT_WAIT 75CLK_COR_SEQ_*_* 75CLK_COR_SEQ_LEN 75CLK_CORRECT_USE 74COMMA_10B_MASK 71CRC_END_OF_PACKET 88CRC_FORMAT 85CRC_START_OF_PACKET 88DEC_MCOMMA_DETECT 71DEC_PCOMMA_DETECT 71DEC_VALID_COMMA_ONLY 71MCOMMA_10B_VALUE 71MCOMMA_DETECT 71PCOMMA_10B_VALUE 71PCOMMA_DETECT 71PRE_EMPHASIS 91RX_BUFFER_USE 74, 90RX_CRC_USE 85RX_DATA_WIDTH 90RX_DECODE_USE 62RX_LOS_INVALID_INCR 77RX_LOS_THRESHOLD 77RX_LOSS_OF_SYNC_FSM 77SERDES_10B 90TERMINATION_IMP 90TX_BUFFER_USE 89TX_CRC_FORCE_VALUE 88TX_CRC_USE 85TX_DATA_WIDTH 90TX_DIFF_CTRL 91Attributes (table) 28BBREFCLKand REF_CLK_V_SEL 31, 41and REFCLKSEL 25, 41and serial speed 39pin numbers 41when & how to use 41Buffers, Fabric Interface 89ports and attributes 89transmitter and elastic (receiver) 89Byte Mapping 37CChannel Bonding (Alignment) 79operation 80ports and attributes 81troubleshooting 83Vitesse channel bonding sequencereceive 66transmit 65Characters, valid (tables) 133Clock Correction (Recovery)clock recovery 73overview 72ports and attributes 74Clock/Data Recovery (CDR) parameters 106Clocking 39clock and data recovery 72clock correction (recovery) 72clock dependency 57clock descriptions 125clock pulse width 128clock ratio 43clock recovery 73clock signals 39clock synthesizer 72clock-to-output delays 127code examples1-byte clock 512-byte clock 444-byte clock 47half-rate clocking scheme 55multiplexed clocking schemewith DCM 56without DCM 56Control Characters, valid (table) 141Coupling, AC and DC 114CRC (Cyclic Redundancy Check) 83generation 84latency 84operation 83ports and attributes 85support limitations 88DData Characters, valid (table) 133Data Path Latency 57Deserializer 68Deterministic Jitter (DJ) 106Differential Receiver 105Differential Trace Design 113HHalf-Rate Clocking Scheme 55HDL Code ExamplesVerilog1-byte clock 532-byte clock 4632-bit alignment design 944-byte clock 49VHDL1-byte clock 512-byte clock 4432-bit alignment design 97Index |
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