56 www.xilinx.com RocketIO™ Transceiver User Guide1-800-255-7778 UG024 (v2.3.2) June 24, 2004Chapter 2: Digital Design ConsiderationsRMultiplexed Clocking Scheme with DCMFollowing configuration of the FPGA, some applications might need to change the frequency of itsREFCLK depending on the protocol used. Figure 2-9 shows how the design can use two differentreference clocks connected to two different DCMs. The clocks are then multiplexed before inputinto the RocketIO transceiver.User logic can be designed to determine during auto negotiation if the reference clock used for thetransceiver is incorrect. If so, the transceiver must then be reset and another reference clock selected.Multiplexed Clocking Scheme without DCMAs with “Example 1b: Two-Byte Clock without DCM”, the DCMs shown in Figure 2-9 may beremoved if TXDATA and RXDATA are not clocked off the FPGA. (See Figure 2-10.) However, thetransceiver must still be reset when clocks are switched.Figure 2-9: Multiplexed REFCLK with DCMREFCLKSELGT_std_2REFCLKREFCLK2REFCLKSELTXUSRCLK2RXUSRCLK2TXUSRCLKRXUSRCLKCLKINCLKFBRSTDCMCLK0CLK0BUFGMUXCLKINCLKFBRSTDCM01Use of 2 DCMs is requiredto maintain correctIBUFG/DCM/BUFGMUX topologyfor clock skew compensationUG024_05a_112202REFCLK_PIBUFGDSREFCLK_NREFCLK2_PREFCLK2_NFigure 2-10: Multiplexed REFCLK without DCMREFCLKSELGT_std_2REFCLKREFCLK2REFCLKSELTXUSRCLK2RXUSRCLK2TXUSRCLKRXUSRCLK01UG024_05b_021503REFCLK_PIBUFGDSBUFGMUXREFCLK_NREFCLK2_PREFCLK2_N
