118 www.xilinx.com Spartan-3A/3AN Starter Kit Board User GuideUG334 (v1.0) May 28, 2007Chapter 14: 10/100 Ethernet Physical Layer Interface REthernet PHY ConnectionsThe FPGA connects to the LAN8700 Ethernet PHY using a standard Media IndependentInterface (MII), as shown in Figure 14-2. A more detailed description of the interfacesignals, including the FPGA pin number, appears in Table 14-1.Figure 14-2: FPGA Connects to Ethernet PHY via MIITable 14-1: FPGA Connections to the LAN83C185 Ethernet PHYSignal Name FPGA PinNumber FunctionE_TXD<4> B2 Transmit Data to the PHY. E_TXD<4> is also the MIITransmit Error.E_TXD<3> F7E_TXD<2> E6E_TXD<1> E7E_TXD<0> F8E_TX_EN D8 Transmit EnableE_TX_CLK E11 Transmit Clock. 25 MHz in 100Base-TX mode and 2.5 MHz in10Base-T mode.E_RXD<4> G10 Receive Data from the PHYE_RXD<3> H9E_RXD<2> G9E_RXD<1> G8E_RXD<0> G7See Table E_TXD<3:0>(E11)FPGAE_TX_ENE_TXD<4>E_TX_CLKTXD[3:0]TXD4/TX_ER/nINITTX_ENTX_CLKSMSC LAN870010/100 Ethernet PHYE_RXD<3:0>E_RX_DVE_MDIOE_MDCE_RX_CLKE_RXD<4>E_CRSE_COLRXD[3:0]RX_DVRXD4/RX_ERRX_CLKCRS/PHYAD4COL_MII_CRS-DVMDCMDIOSee Table(H10)(G10)(C12)(H12)(G12)(D10)(E10)(D8)(B2)RJ-45Connector25.000 MHzUG334_c14_02_052407E_NRST nRST(D15)(integratedmagnetics)
