Xilinx Spartan-3A User Manual

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Spartan-3A/3AN Starter Kit Board User Guide www.xilinx.com 133UG334 (v1.0) May 28, 2007Connectorless Debugging Port Landing Pads (J34)RUCF Location ConstraintsFigure 15-11 provides the User Constraint File (UCF) constraints for the accessory headers,including the I/O pin assignment and the I/O standard used.Connectorless Debugging Port Landing Pads (J34)Landing pads for a connectorless debugging port are provided as the J34 header. There isno physical connector on the board. Instead a connectorless probe, such as those availablefrom Agilent, provides an interface to a logic analyzer. This debugging port is intendedprimarily for the Xilinx ChipScope Pro software with the Agilent FPGA Dynamic Probe. Itcan, however, be used with either the Agilent or Tektronix probes, without the ChipScopesoftware, using FPGA Editor’s probe command.• Xilinx ChipScope Pro Toolwww.xilinx.com/ise/optional_prod/cspro.htm• Agilent B4655A FPGA Dynamic Probe for Logic Analyzerwww.home.agilent.com/USeng/nav/-536902581.0/pc.html• Agilent 5404A/6A Pro Series Soft Touch Connectorwww.home.agilent.com/cgi-bin/pub/agilent/Product/cp_Product.jsp?NAV_ID=-536898227.0.00• Tektronix P69xx Probe Modules with D-Max Technologywww.tek.com/products/accessories/logic_analyzers/p6800_p6900.htmlFigure 15-11: UCF Location Constraints for Six-Pin Accessory Headers# ==== 6-pin header J18 ====# These four connections are shared with the FX2 connectorNET "J18_IO<1>" LOC = "AA21" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J18_IO<2>" LOC = "AB21" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J18_IO<3>" LOC = "AA19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J18_IO<4>" LOC = "AB19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;# ==== 6-pin header J19 ====# These four connections are shared with the FX2 connector# These four connections go to through-hole pads, not to a connector.NET "J19_IO<1>" LOC = "Y18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J19_IO<2>" LOC = "W18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J19_IO<3>" LOC = "V17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J19_IO<4>" LOC = "W17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;# ==== 6-pin header J20 ====# These four connections are shared with the FX2 connectorNET "J20_IO<1>" LOC = "V14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J20_IO<2>" LOC = "V15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J20_IO<3>" LOC = "W16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "J20_IO<4>" LOC = "V16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;