34 www.xilinx.com Spartan-3A/3AN Starter Kit Board User GuideUG334 (v1.0) May 28, 2007Chapter 3: Clock Sources RClock ConnectionsEach of the clock inputs connect directly to a global buffer input. As shown in Table 3-1,each of the clock inputs also optimally connects to an associated DCM.Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time.However, both inputs are available as clock inputs.50 MHz On-Board OscillatorThe board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillatoris accurate to ±2500 Hz or ±50 ppm.Auxiliary Clock Oscillator SocketA 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket. The providedeight-pin socket accepts clock oscillators that fit the eight-pin DIP (8DIP) footprint.Substitute the oscillator in this socket if the FPGA application requires a frequency otherthan 50 MHz or 133 MHz. Alternatively, use the FPGA’s Digital Clock Manager (DCM) togenerate or synthesize other frequencies from the on-board 50 MHz or 133 MHz oscillator.Caution! Be aware of the pin 1 orientation on the crystal oscillator when installing it in theassociated socket.SMA Clock Input or Output ConnectorTo provide a clock from an external source, connect the input clock signal to the SMAconnector. The FPGA can also generate a single-ended clock output or other high-speedsignal on the SMA clock connector for an external device.UCF ConstraintsThe clock input sources require two different types of constraints. The location constraintsdefine the I/O pin assignments and I/O standards. The period constraints define the clockperiod—and consequently the clock frequency—and the duty cycle of the incoming clocksignal.LocationFigure 3-2 provides the UCF constraints for the three clock input sources, including theI/O pin assignment and the I/O standard used.Table 3-1: Clock Inputs and Associated Global Buffers and DCMsClock Input FPGA Pin I/O Bank Global Buffer Associated DCM LOCCLK_50MHZ E12 0 GCLK5 Top Right DCM_X2Y3CLK_AUX V12 2 GCLK2 Bottom Right DCM_X2Y0CLK_SMA U12 2 GCLK3
