80 www.xilinx.com Spartan-3A/3AN Starter Kit Board User GuideUG334 (v1.0) May 28, 2007Chapter 10: Digital-to-Analog Converter (DAC) RInterface SignalsTable 10-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,DAC_OUT, and SPI_SCK signals are shared with other devices on the SPI bus. TheDAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal isthe active-Low, asynchronous reset input to the DAC.The serial data output from the DAC is primarily used to cascade multiple DACs. Thissignal can be ignored in most applications although it does demonstrate full-duplexcommunication over the SPI bus.SPI Communication DetailsFigure 10-3 shows a detailed example of the SPI bus timing. Each bit is transmitted orreceived relative to the SPI_SCK clock signal. The bus is fully static and supports clockrates up to the maximum of 50 MHz. However, check all timing parameters using theLTC2624 data sheet if operating at or close to the maximum speed.Figure 10-2: Digital-to-Analog Connection SchematicsHeader J5DAC A12DAC B12DAC C1212SPI_MOSIDAC_CSSPI_SCKDAC_CLRCS/LDSDISCKCLRSDODAC_OUT(V7) (AB14)(AA20)(AB13)(W7)3.3V ABCDGNDVCCREF AREF BREF CREF DVOUTAVOUTBVOUTCVOUTDFPGADAC DLTC 2624 DACSPI Control Interface (3.3V)UG334_c10_02_052407Programmable referencesupplied by adjustableLP3906 regulator, IC18.3.3V by default.Table 10-1: DAC Interface SignalsSignal FPGA Pin Direction DescriptionSPI_MOSI AB14 FPGAÆDAC Serial data: Master Output, Slave InputDAC_CS W7 FPGAÆDAC Active-Low chip-select. Digital-to-analogconversion starts when this signal returnsHigh.SPI_SCK AA20 FPGAÆDAC ClockDAC_CLR AB13 FPGAÆDAC Asynchronous, active-Low reset inputDAC_OUT V7 FPGAÅDAC Serial data from the DAC
