76 www.xilinx.com Spartan-3A/3AN Starter Kit Board User GuideUG334 (v1.0) May 28, 2007Chapter 9: Analog Capture Circuit RFigure 9-7 shows detailed transaction timing. The AD_CONV signal is not a traditional SPIslave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leavesthe ADC_OUT signal in the high-impedance state. As shown in Figure 9-6, use a 34-cyclecommunications sequence. The ADC 3-states its data output for two clock cycles beforeand after each 14-bit data transfer.UCF Location ConstraintsFigure 9-8 provides the User Constraint File (UCF) constraints for the amplifier interface,including the I/O pin assignment and I/O standard used.Figure 9-6: Analog-to-Digital Conversion InterfaceFPGAMasterD 1 D 2 D 3D 0 D 5 D 6 D 7D 4 D 9 D 10 D 11D 8 D 13D 12 D 1 D 2 D 3D 0 D 5 D 6 D 7D 4 D 9 D 10 D 11D 8 D 13D 12Z ZZ1313 0 0ADC_OUTSPI_SCKAD_CONV13Channel 0 Channel 0Channel 1SamplepointSamplepointConverted data is presented with a latency of one sample.The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.The converted values is then presented after the next AD_CONV pulse.AD_CONVSPI_SCKADC_OUTSlave: LTC1407A-1 A/D ConverterChannel 1 Channel 0UG334_c9_06_052407Figure 9-7: Detailed SPI Timing to ADCSPI_SCKAD_CONVADC_OUT 13 12 11High-Z2 1 0 High-Z6ns8ns3ns4ns min19.6ns min45ns min31 2 3344325 6333130The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cyclesChannel 1Channel 0SPI_SCKAD_CONVADC_OUTUG330_c10_06_032007Figure 9-8: UCF Location Constraints for the ADC InterfaceNET "AD_CONV" LOC = "Y6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 12 ;NET "AD_DOUT" LOC = "D16" | IOSTANDARD = LVTTL ;
