Xilinx Spartan-3A User Manual

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82 www.xilinx.com Spartan-3A/3AN Starter Kit Board User GuideUG334 (v1.0) May 28, 2007Chapter 10: Digital-to-Analog Converter (DAC) RThe FPGA first sends eight dummy or don’t care bits, followed by a four-bit command. Themost commonly used command with the board is COMMAND[3:0] = 0011 binary, whichimmediately updates the selected DAC output with the specified data value. Following thecommand, the FPGA selects one or all the DAC output channels via a four-bit addressfield. Following the address field, the FPGA sends a 12-bit unsigned data value that theDAC converts to an analog value on the selected output(s). Finally, four additional dummyor don’t care bits pad the 32-bit command word.Specifying the DAC Output VoltageAs shown in Figure 10-2, each DAC output level is the analog equivalent of a 12-bitunsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.The voltage on a specific output is generally described in Equation 10-1. The referencevoltage, V REFERENCE, is different between the four DAC outputs. Channels A and B use a3.3V reference voltage. Channels C and D have a separate reference voltage, nominally also3.3V, supplied by the LP3906 regulator designated as IC18. The reference voltage forChannels C and D can be modified, as described in “I 2 C Voltage Adjustment Interface,”page 140.The reference voltages themselves have a ±5% tolerance, so there are slight correspondingvariances in the output voltage.Equation 10-1UCF Location ConstraintsFigure 10-5 provides the UCF constraints for the DAC interface, including the I/O pinassignment and the I/O standard used.Related ResourcesRefer to the following links for additional information:• LTC2624 Quad DAC Data Sheethttp://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170• Xilinx PicoBlaze Soft Processorhttp://www.xilinx.com/picoblaze• Digilent, Inc. Peripheral Moduleshttp://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=PeripheralV OUTD 11:0[ ]4 096,--------------------- V REFERENCE×=Figure 10-5: UCF Location Constraints for the DAC InterfaceNET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;NET "DAC_OUT" LOC = "V7" | IOSTANDARD = LVTTL ;