Xilinx Spartan-3A User Manual
Also see for Spartan-3A DSP FPGA Series: DatasheetUser guideGetting startedTechnical reference guideUser guide
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140 www.xilinx.com Spartan-3A/3AN Starter Kit Board User GuideUG334 (v1.0) May 28, 2007Chapter 17: Voltage Supplies RCaution! If the meter offers various current ranges, always start with the largest range first.Passing too large a current through a meter may damage it.• Reapply power to the board.• Record the current measurements across the jumper.• If the FPGA design supports the power-saving Suspend mode, measure the currentwith the SUSPEND switch (see “SUSPEND Switch,” page 26) set in both the “RUN”and “SUSPEND” positions. The default FPGA application shipped with the StarterKit board does use the Suspend mode. For additional information on the Suspendmode, see the “Power Management Solutions” chapter in UG331: Spartan-3 GenerationFPGA User Guide.• Convert the current measurement (Amperes or mA) to a power measurement (Wattsor mW), by multiplying the measured result by the supply voltage.I 2C Voltage Adjustment InterfaceEach LP3906 regulator has an two-wire, I 2 C serial interface that optionally controls variousfunctions, such as the regulator output voltage. As indicated in Table 17-3, the I2 C interfacecan be controlled by the FPGA application using the I/O pins indicated or by someexternal controller using the through-hole mounting pads provided on the board, shownin Figure 17-1.Possible ApplicationsFor experimentation purposes only, Xilinx only recommends adjusting the two supplieslisted below:• By default, the V CCAUX supply to the FPGA is set to 3.3V, as required for Spartan-3ANFPGAs. On Spartan-3A FPGAs, V CCAUX can be either 2.5V or 3.3V, with potentiallylower power consumption at 2.5V. Consequently, VCCAUX can be reduced to 2.5V byadjusting the LDO1 output on the LP3906 regulator designated IC19. Thecorresponding I2 C control signals are REG1_SCL and REG1_SDA.• By default, the reference voltage to Channels C and D on the D/A converter is 3.3V.However, this voltage can be adjusted to between 1.0V and 3.3V by controlling theLDO1 output on IC18. The corresponding I2 C control signals are REG2_SCL andREG2_SDA. See Chapter 10, “Digital-to-Analog Converter (DAC)” for additionalinformation.Table 17-3: I2 C Voltage Adjustment Interface to RegulatorRegulator I2C Control Input FPGA Connection Through-HoleConnectionIC18SCL REG2_SCL(D11) REG2-SCLSDA REG2_SDA(F13) REG2-SDAIC19SCL REG1_SCL(E13) REG1-SCLSDA REG1_SDA(D13) REG1-SDA |
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