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Nuvoton Mini51 Series manuals

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Mini51 Series

Brand: Nuvoton | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. GENERAL DESCRIPTION
  10. FEATURES
  11. PARTS INFORMATION LIST AND PIN CONFIGURATION
  12. PIN CONFIGURATION
  13. QFN 33-pin
  14. Pin Description
  15. Table 3.3-1 NuMicro Mini51 Series Pin Description
  16. BLOCK DIAGRAM
  17. FUNCTIONAL DESCRIPTION
  18. System Memory Map
  19. Nested Vectored Interrupt Controller (NVIC)
  20. Table 5.2-1 Exception Model
  21. Vector Table
  22. NVIC Operation
  23. NVIC Control Registers
  24. Interrupt Source Control Registers
  25. System Manager
  26. Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram
  27. Memory Mapping Table
  28. System Manager Control Registers
  29. Clock Controller
  30. System Clock and SysTick Clock
  31. AHB Clock Source Selection
  32. Peripheral Clock Source Selection
  33. Table 5.4-1 Peripherals Engine Clock Source Selection Table
  34. Power-down Mode Clock
  35. Frequency Divider Output
  36. Clock Control Register Map
  37. Clock Control Register
  38. Table 5.4-2 Power-down Mode Control Table
  39. Comparator Controller (CMPC)
  42. Comparator Reference Voltage (CRV)
  43. Register Map
  44. Register Description
  45. Analog-to-Digital Converter (ADC) Controller
  47. Figure 5.6-2 ADC Clock Control
  48. Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram
  49. ADC Register Map
  50. ADC Register
  51. Flash Memory Controller (FMC)
  52. Figure 5.7-1 Flash Memory Control Block Diagram
  54. Figure 5.7-2 Flash Memory Organization
  55. Table 5.7-2 Boot Selection Table
  56. Figure 5.7-3 Flash Memory Structure
  57. Table 5.7-4 Data Flash Configuration Example
  58. Figure 5.7-4 ISP Procedure
  59. Figure 5.7-5 ISP Operation Flow
  60. Table 5.7-5 ISP Command Table
  61. Flash Control Register Map
  62. Flash Control Register
  63. General Purpose I/O
  64. Figure 5.8-1 Push-Pull Output
  65. Figure 5.8-3 Quasi-bidirectional I/O Mode
  66. Port 0-5 Control Register Map
  67. Port 0-5 Control Register
  68. Overview
  69. Figure 5.9-3 Master Transmits Data to Slave
  70. Figure 5.9-4 Master Reads Data from Slave
  71. Register Mapping
  73. Operation Modes
  74. Figure 5.9-10 Legend for the Following Five Figures
  75. Figure 5.9-11 Master Transmitter Mode
  76. Figure 5.9-12 Master Receiver Mode
  77. Figure 5.9-13 Slave Transmitter Mode
  78. Figure 5.9-14 Slave Receiver Mode
  79. Figure 5.9-15 GC Mode
  80. Enhanced PWM Generator
  81. Figure 5.10-1 Application Circuit Diagram
  82. PWM Block Diagram
  83. Figure 5.10-4 PWM Generator 2 Architecture Diagram
  84. PWM Function
  85. Figure 5.10-6 Edge-aligned PWM
  86. Figure 5.10-8 Edge-aligned Flow Diagram
  87. Figure 5.10-9 Legend of Internal Comparator Output of PWM-Timer
  88. Figure 5.10-11 Center-aligned Mode
  89. Figure 5.10-12 PWM Center-aligned Waveform Output
  90. Figure 5.10-13 Center-aligned Flow Diagram (INT_TYPE = 0)
  91. Figure 5.10-14 PWM Double Buffering Illustration
  92. PWM Operation Modes
  93. Polarity Control
  94. Figure 5.10-17 Initial State and Polarity Control with Rising Edge Dead-zone Insertion
  95. PWM for Motor Control Interrupt Architecture
  96. PWM Controller Register Map
  97. PWM Controller Register
  98. Serial Peripheral Interface (SPI) Controller
  100. Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction
  101. Figure 5.11-6 Byte Reorder
  102. Figure 5.11-8 Variable Serial Clock Frequency
  103. Figure 5.11-9 SPI Timing in Master Mode
  104. Figure 5.11-10 SPI Timing in Master Mode (Alternate Phase of SPICLK)
  105. Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
  106. SPI Serial Interface Control Register Map
  108. Timer Controller
  111. Figure 5.12-3 Continuous Counting Mode
  112. Table 5.12-1 Input Capture Mode Operation
  115. UART Interface Controller
  118. Figure 5.13-2 UART Block Diagram
  120. Figure 5.13-4 IrDA Block Diagram
  121. Figure 5.13-5 IrDA TX/RX Timing Diagram
  122. Figure 5.13-6 Structure of RS-485 Frame
  123. Registers Map
  125. Table 5.13-3 UART Interrupt Sources and Flags Table In Software Mode
  126. Table 5.13-4 UART Baud Rate Setting Table
  127. Watchdog Timer
  129. Figure 5.14-3 Watchdog Timer Block Diagram
  130. Watchdog Timer Control Registers Map
  134. System Timer (SysTick)
  135. System Timer Control Register Map
  136. System Timer Control Register
  137. System Control Registers
  138. System Control Register
  139. APPLICATION CIRCUIT
  140. ELECTRICAL CHARACTERISTICS
  141. DC Electrical Characteristics
  142. AC Electrical Characteristics
  143. External 32.768 KHz XTAL Oscillator
  144. Internal 10 KHz RC Oscillator
  145. Analog Characteristics
  146. Analog Comparator Reference Voltage (CRV)
  147. Flash Memory Characteristics
  148. PACKAGE DIMENSION
  149. pin QFN (4mm x 4mm)
  150. pin QFN (5mm x 5mm)
  151. REVISION HISTORY
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