Nuvoton Mini51 Series Technical Reference Manual

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Nuvoton Mini51 Series Technical Reference Manual Manual pdf 6 page image

NuMicro™ Mini51 Technical Reference ManualFeb 9, 2012 Page 6 of 342 Revision V1.03NUMICRO™ MINI51 TECHNICAL REFERENCE MANUALList of FiguresFigure 3.1-1 NuMicro Mini51 Series Product Selection Guide .................................................... 14Figure 3.2-1 NuMicro Mini51 Series LQFP 48-pin Assignment .................................................. 15Figure 3.2-2 NuMicro Mini51 Series QFN 33-pin Assignment .................................................... 16Figure 4.1-1 NuMicro Mini51 Series Block Diagram ................................................................... 21Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram ............................................... 48Figure 5.4-1 Clock Generator Block Diagram ................................................................................ 75Figure 5.4-2 System Clock Block Diagram .................................................................................... 76Figure 5.4-3 SysTick Clock Control Block Diagram ....................................................................... 76Figure 5.4-4 AHB Clock Source for HCLK ..................................................................................... 77Figure 5.4-5 Peripherals Clock Source Selection for PCLK........................................................... 78Figure 5.4-6 Clock Source of Frequency Divider ........................................................................... 81Figure 5.4-7 Block Diagram of Frequency Divider ......................................................................... 81Figure 5.5-1 Analog Comparator Block Diagram ........................................................................... 99Figure 5.5-2 Comparator Controller Interrupt Sources ................................................................ 100Figure 5.5-3 Comparator Reference Voltage Block Diagram ...................................................... 101Figure 5.6-1 ADC Controller Block Diagram ................................................................................ 108Figure 5.6-2 ADC Clock Control ................................................................................................... 109Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram ..................................................... 110Figure 5.6-4 A/D Controller Interrupt ............................................................................................ 110Figure 5.7-1 Flash Memory Control Block Diagram ..................................................................... 122Figure 5.7-2 Flash Memory Organization ..................................................................................... 124Figure 5.7-3 Flash Memory Structure .......................................................................................... 126Figure 5.7-4 ISP Procedure.......................................................................................................... 130Figure 5.7-5 ISP Operation Flow .................................................................................................. 131Figure 5.8-1 Push-Pull Output ...................................................................................................... 143Figure 5.8-2 Open-Drain Output .................................................................................................. 143Figure 5.8-3 Quasi-bidirectional I/O Mode ................................................................................... 144Figure 5.9-1 Bus Timing ............................................................................................................... 167Figure 5.9-2 I2C Protocol .............................................................................................................. 168Figure 5.9-3 Master Transmits Data to Slave .............................................................................. 168Figure 5.9-4 Master Reads Data from Slave ................................................................................ 169Figure 5.9-5 START and STOP Condition ................................................................................... 169Figure 5.9-6 Bit Transfer on the I2C Bus ...................................................................................... 170Figure 5.9-7 Acknowledge on the I2C Bus ................................................................................... 171Figure 5.9-8 I2C Data Shifting Direction ....................................................................................... 172