NuMicro™ Mini51 Technical Reference ManualFeb 9, 2012 Page 167 of 342 Revision V1.03NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL5.9 I2C Serial Interface Controller (Master/Slave)5.9.1 OverviewI2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of dataexchange between devices. The I2C standard is a true multi-master bus including collisiondetection and arbitration that prevents data corruption if two or more masters attempt to control thebus simultaneously. Serial 8-bit oriented bi-directional data transfers can be made up 1.0 Mbps.Data is transferred between a master and a slave synchronously to SCL on the SDA line on abyte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bitwith the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit issampled during the high period of SCL; therefore, the SDA line may be changed only during thelow period of SCL and must be held stable during the high period of SCL. A transition on the SDAline while SCL is high is interpreted as a command (START or STOP). Please refer to thefollowing figure for more detailed I2C BUS Timing.tBUFSTOPSDASCLSTARTtHD;STAtLOWtHD;DATtHIGHtftSU;DATRepeatedSTARTtSU;STA tSU;STOSTOPtrFigure 5.9-1 Bus TimingThe device‟s on-chip I2C logic provides the serial interface that meets the I2C bus standard modespecification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENSIin I2CON should be set to “1”. The I2C hardware interfaces to the I2C bus via two pins: SDA (P3.4,serial data line) and SCL (P3.5, serial clock line). Since the pull-up resistor is needed for Pin P3.4and P3.5 for I2C operation as these are open-drain pins. When the I/O pins are used as I2C port,user must set the pins function to I2C in advance.5.9.2 FeaturesThe I2C bus uses two wires (SDA and SCL) to transfer information between devices connected tothe bus. The main features of the bus are: Supports Master/Slave mode Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serialdata on the bus Serial clock synchronization allowing devices with different bit rates to communicatevia one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend andresume serial transfer Built-in 14-bit time-out counter that requests the I2C interrupt if the I2C bus hangs up
