Nuvoton Mini51 Series Technical Reference Manual

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Nuvoton Mini51 Series Technical Reference Manual Manual pdf 7 page image

NuMicro™ Mini51 Technical Reference ManualFeb 9, 2012 Page 7 of 342 Revision V1.03NUMICRO™ MINI51 TECHNICAL REFERENCE MANUALFigure 5.9-9 I2C Time-out Count Block Diagram .......................................................................... 173Figure 5.9-10 Legend for the Following Five Figures .................................................................. 185Figure 5.9-11 Master Transmitter Mode ....................................................................................... 186Figure 5.9-12 Master Receiver Mode ........................................................................................... 187Figure 5.9-13 Slave Transmitter Mode ......................................................................................... 188Figure 5.9-14 Slave Receiver Mode ............................................................................................. 189Figure 5.9-15 GC Mode................................................................................................................ 190Figure 5.10-1 Application Circuit Diagram ................................................................................... 192Figure 5.10-2 PWM Block Diagram .............................................................................................. 193Figure 5.10-3 PWM Generator 0 Architecture Diagram ............................................................... 193Figure 5.10-4 PWM Generator 2 Architecture Diagram ............................................................... 194Figure 5.10-5 PWM Generator 4 Architecture Diagram ............................................................... 194Figure 5.10-6 Edge-aligned PWM ................................................................................................ 196Figure 5.10-7 PWM Edge-aligned Waveform Output .................................................................. 196Figure 5.10-8 Edge-aligned Flow Diagram .................................................................................. 197Figure 5.10-9 Legend of Internal Comparator Output of PWM-Timer ......................................... 198Figure 5.10-10 PWM Timer Operation Timing ............................................................................. 198Figure 5.10-11 Center-aligned Mode ........................................................................................... 199Figure 5.10-12 PWM Center-aligned Waveform Output .............................................................. 200Figure 5.10-13 Center-aligned Flow Diagram (INT_TYPE = 0) ................................................... 201Figure 5.10-14 PWM Double Buffering Illustration ....................................................................... 202Figure 5.10-15 PWM Controller Output Duty Ratio ...................................................................... 202Figure 5.10-16 Dead-zone Insertion ............................................................................................ 203Figure 5.10-17 Initial State and Polarity Control with Rising Edge Dead-zone Insertion ............. 205Figure 5.10-18 Motor Control PWM Architecture ......................................................................... 206Figure 5.11-1 SPI Block Diagram ................................................................................................. 228Figure 5.11-3 SPI Slave Mode Application Block Diagram .......................................................... 229Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction .................................................... 231Figure 5.11-5 Word Suspend Mode ............................................................................................. 231Figure 5.11-6 Byte Reorder .......................................................................................................... 232Figure 5.11-7 Byte Suspend Mode .............................................................................................. 232Figure 5.11-8 Variable Serial Clock Frequency ........................................................................... 233Figure 5.11-9 SPI Timing in Master Mode ................................................................................... 234Figure 5.11-10 SPI Timing in Master Mode (Alternate Phase of SPICLK) .................................. 235Figure 5.11-11 SPI Timing in Slave Mode ................................................................................... 235Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK) .................................... 236