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Nuvoton Mini51 Series Technical Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. GENERAL DESCRIPTION
  10. FEATURES
  11. PARTS INFORMATION LIST AND PIN CONFIGURATION
  12. PIN CONFIGURATION
  13. QFN 33-pin
  14. Pin Description
  15. Table 3.3-1 NuMicro Mini51 Series Pin Description
  16. BLOCK DIAGRAM
  17. FUNCTIONAL DESCRIPTION
  18. System Memory Map
  19. Nested Vectored Interrupt Controller (NVIC)
  20. Table 5.2-1 Exception Model
  21. Vector Table
  22. NVIC Operation
  23. NVIC Control Registers
  24. Interrupt Source Control Registers
  25. System Manager
  26. Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram
  27. Memory Mapping Table
  28. System Manager Control Registers
  29. Clock Controller
  30. System Clock and SysTick Clock
  31. AHB Clock Source Selection
  32. Peripheral Clock Source Selection
  33. Table 5.4-1 Peripherals Engine Clock Source Selection Table
  34. Power-down Mode Clock
  35. Frequency Divider Output
  36. Clock Control Register Map
  37. Clock Control Register
  38. Table 5.4-2 Power-down Mode Control Table
  39. Comparator Controller (CMPC)
  40. Comparator Reference Voltage (CRV)
  41. Register Map
  42. Register Description
  43. Analog-to-Digital Converter (ADC) Controller
  44. Figure 5.6-2 ADC Clock Control
  45. Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram
  46. ADC Register Map
  47. ADC Register
  48. Flash Memory Controller (FMC)
  49. Figure 5.7-1 Flash Memory Control Block Diagram
  50. Figure 5.7-2 Flash Memory Organization
  51. Table 5.7-2 Boot Selection Table
  52. Figure 5.7-3 Flash Memory Structure
  53. Table 5.7-4 Data Flash Configuration Example
  54. Figure 5.7-4 ISP Procedure
  55. Figure 5.7-5 ISP Operation Flow
  56. Table 5.7-5 ISP Command Table
  57. Flash Control Register Map
  58. Flash Control Register
  59. General Purpose I/O
  60. Figure 5.8-1 Push-Pull Output
  61. Figure 5.8-3 Quasi-bidirectional I/O Mode
  62. Port 0-5 Control Register Map
  63. Port 0-5 Control Register
  64. Overview
  65. Figure 5.9-3 Master Transmits Data to Slave
  66. Figure 5.9-4 Master Reads Data from Slave
  67. Register Mapping
  68. Operation Modes
  69. Figure 5.9-10 Legend for the Following Five Figures
  70. Figure 5.9-11 Master Transmitter Mode
  71. Figure 5.9-12 Master Receiver Mode
  72. Figure 5.9-13 Slave Transmitter Mode
  73. Figure 5.9-14 Slave Receiver Mode
  74. Figure 5.9-15 GC Mode
  75. Enhanced PWM Generator
  76. Figure 5.10-1 Application Circuit Diagram
  77. PWM Block Diagram
  78. Figure 5.10-4 PWM Generator 2 Architecture Diagram
  79. PWM Function
  80. Figure 5.10-6 Edge-aligned PWM
  81. Figure 5.10-8 Edge-aligned Flow Diagram
  82. Figure 5.10-9 Legend of Internal Comparator Output of PWM-Timer
  83. Figure 5.10-11 Center-aligned Mode
  84. Figure 5.10-12 PWM Center-aligned Waveform Output
  85. Figure 5.10-13 Center-aligned Flow Diagram (INT_TYPE = 0)
  86. Figure 5.10-14 PWM Double Buffering Illustration
  87. PWM Operation Modes
  88. Polarity Control
  89. Figure 5.10-17 Initial State and Polarity Control with Rising Edge Dead-zone Insertion
  90. PWM for Motor Control Interrupt Architecture
  91. PWM Controller Register Map
  92. PWM Controller Register
  93. Serial Peripheral Interface (SPI) Controller
  94. Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction
  95. Figure 5.11-6 Byte Reorder
  96. Figure 5.11-8 Variable Serial Clock Frequency
  97. Figure 5.11-9 SPI Timing in Master Mode
  98. Figure 5.11-10 SPI Timing in Master Mode (Alternate Phase of SPICLK)
  99. Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
  100. SPI Serial Interface Control Register Map
  101. Timer Controller
  102. Figure 5.12-3 Continuous Counting Mode
  103. Table 5.12-1 Input Capture Mode Operation
  104. UART Interface Controller
  105. Figure 5.13-2 UART Block Diagram
  106. Figure 5.13-4 IrDA Block Diagram
  107. Figure 5.13-5 IrDA TX/RX Timing Diagram
  108. Figure 5.13-6 Structure of RS-485 Frame
  109. Registers Map
  110. Table 5.13-3 UART Interrupt Sources and Flags Table In Software Mode
  111. Table 5.13-4 UART Baud Rate Setting Table
  112. Watchdog Timer
  113. Figure 5.14-3 Watchdog Timer Block Diagram
  114. Watchdog Timer Control Registers Map
  115. System Timer (SysTick)
  116. System Timer Control Register Map
  117. System Timer Control Register
  118. System Control Registers
  119. System Control Register
  120. APPLICATION CIRCUIT
  121. ELECTRICAL CHARACTERISTICS
  122. DC Electrical Characteristics
  123. AC Electrical Characteristics
  124. External 32.768 KHz XTAL Oscillator
  125. Internal 10 KHz RC Oscillator
  126. Analog Characteristics
  127. Analog Comparator Reference Voltage (CRV)
  128. Flash Memory Characteristics
  129. PACKAGE DIMENSION
  130. pin QFN (4mm x 4mm)
  131. pin QFN (5mm x 5mm)
  132. REVISION HISTORY
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Mini51 Series
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