NuMicro™ Mini51 Technical Reference ManualFeb 9, 2012 Page 109 of 342 Revision V1.03NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL5.6.4.1 ADC Clock GeneratorThe maximum sampling rate is up to 150 K. The ADC engine has clock source selected by 2-bitADC_S (CLKSEL1[3:2]), the ADC clock frequency is divided by an 8-bit prescaler with the formula:The ADC clock frequency = (ADC clock source frequency) / (ADC_N+1);where the 8-bit ADC_N is located in register CLKDIV[23:16].In general, software can set ADC_S and ADC_N to get 6 MHz or slightly less.11100100Reserved4~24 MHz22.1184 MHzADC_S (CLKSEL1[3:2])ADC_EN(APBCLK[28])ADC_CLK1/(ADC_N + 1)ADC_N(CLKDIV[23:16])HCLKFigure 5.6-2 ADC Clock Control5.6.4.2 OperationA/D conversion is performed only once on the specified single channel. The operation is asfollows:1. A/D conversion will be started when the ADST bit of ADCR is set to “1” by software or externaltrigger input.2. When A/D conversion is finished, the result is stored in the A/D data register (ADDR).3. The ADF bit of ADSR register will be set to “1”. If the ADIE bit of ADCR register is set to “1”,the ADC interrupt will be asserted.4. The ADST bit remains “1” during A/D conversion. When A/D conversion ends, the ADST bit isautomatically cleared to “0” and the A/D converter enters in idle state.Note: If software enables more than one channel, the channel with the lowest number will beselected and the other enabled channels will be ignored.5.6.4.3 External Trigger Input Sampling and A/D Conversion TimeA/D conversion can be triggered by external pin request. When the ADCR.TRGEN is set to high,ADC external trigger function is enabled and trigger input source is from the STADC pin. Softwarecan set TRGCOND to select trigger condition is falling or rising edge. An 8-bit sampling counter isused to deglitch. If edge trigger condition is happened, the high and low state must be kept at least4 PLCKs. Pulse that is shorter than this specification will be ignored.5.6.4.4 Conversion Result Monitor by Compare Mode FunctionThe NuMicro Mini51 series controller provides two sets of compare registers, ADCMPR0 and
