NuMicro™ Mini51 Technical Reference ManualFeb 9, 2012 Page 233 of 342 Revision V1.03NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL01Byte reorder function active. Insert a clock idle interval among eachbyte.The setting of TX_BIT_LEN must be configured as 0x00 (32 bits/word).10 Bytes reorder function active but no clock idle interval among eachbyte.11No bytes reorder function but insert a clock idle interval among eachbyte.The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word).Table 5.11-1 Byte Order and Byte Clock Idle Internal Conditions5.11.4.14 InterruptEach SPI controller can generate an individual interrupt source when data transfer is finished andthe respective interrupt event flag IF (SPI_CNTRL[16]) will be set. The interrupt event flag willgenerate an interrupt to CPU if the interrupt enable IE (SPI_CNTRL[17]) is set. The interrupt eventflag IF can be cleared only by writing “1” to it.5.11.4.15 Variable Serial Clock FrequencyIn Master mode, the output of serial clock can be programmed as variable frequency pattern if theVariable Clock Enable bit VARCLK_EN (SPI_CNTRL[23]) is enabled. The frequency patternformat is defined in VARCLK (SPI_VARCLK[31:0]) register. If the bit content of VARCLK is „0‟ theoutput frequency is in accordance with the DIVIDER (SPI_DIVIDER[15:0]) and if the bit content ofVARCLK is “1”, the output frequency is in accordance with the DIVIDER2 (SPI_DIVIDER[31:16]).The following figure is the timing relationship among the serial clock (SPICLK), VARCLK, DIVIDERand DIVIDER2 registers. A two-bit combination in the VARCLK defines one clock cycle. The bitfield VARCLK[31:30] defines the first clock cycle of SPICLK. The bit field VARCLK[29:28] definesthe second clock cycle of SPICLK, and so on. The clock source selections are defined in VARCLKand it must be set to 1 cycle before the next clock option. For example, if there are 5 CLK1 cyclesin SPICLK, the VARCLK shall set 9 ”0” in the MSB of VARCLK. The 10th shall be set as ”1" inorder to switch the next clock source as CLK2. Note that when enabling the VARCLK_EN bit, thesetting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode only).00000000011111111111111110000111SPICLKVARCLKCLK1 (DIVIDER)CLK2 (DIVIDER2)Figure 5.11-8 Variable Serial Clock Frequency
