Weak-end infeed logic................................................................ 403Setting guidelines............................................................................ 404Current reverse logic.................................................................. 404Weak-end infeed logic................................................................ 405Local acceleration logic ZCLCPLAL..................................................... 405Identification.................................................................................... 405Application....................................................................................... 405Setting guidelines............................................................................ 406Scheme communication logic for residual overcurrent protectionECPSCH (85)....................................................................................... 407Identification.................................................................................... 407Application....................................................................................... 407Setting guidelines............................................................................ 408Current reversal and weak-end infeed logic for residual overcurrentprotection ECRWPSCH (85).................................................................408Identification.................................................................................... 408Application....................................................................................... 409Fault current reversal logic......................................................... 409Weak-end infeed logic................................................................ 410Setting guidelines............................................................................ 410Current reversal..........................................................................410Weak-end infeed........................................................................ 411Section 13 Logic..................................................................................413Tripping logic common 3-phase output SMPPTRC (94).......................413Identification.................................................................................... 413Application....................................................................................... 413Three-pole tripping .................................................................... 413Lock-out......................................................................................414Blocking of the function block..................................................... 414Setting guidelines............................................................................ 415Tripping logic phase segregated output SPTPTRC 94.........................415Identification.................................................................................... 415Application....................................................................................... 415Single- and/or three-pole tripping............................................... 416Lock out...................................................................................... 417Blocking of the function block..................................................... 417Setting guidelines............................................................................ 417Trip matrix logic TMAGGIO.................................................................. 418Identification.................................................................................... 418Table of contents13Application manual
