3-30 D30 Line Distance Protection System GE Multilin3.3 DIRECT INPUT/OUTPUT COMMUNICATIONS 3 HARDWARE33.3DIRECT INPUT/OUTPUT COMMUNICATIONS 3.3.1 DESCRIPTIONThe direct inputs and outputs feature makes use of the type 7 series of communications modules, which allow direct mes-saging between UR devices. These communications modules are outlined in the table later in this section.The communications channels are normally connected in a ring configuration as shown in the following figure. The trans-mitter of one module is connected to the receiver of the next module. The transmitter of this second module is then con-nected to the receiver of the next module in the ring. This is continued to form a communications ring. The figure illustratesa ring of four UR-series relays with the following connections: UR1-Tx to UR2-Rx, UR2-Tx to UR3-Rx, UR3-Tx to UR4-Rx,and UR4-Tx to UR1-Rx. A maximum of 16 URs can be connected in a single ringFigure 3–29: DIRECT INPUT AND OUTPUT SINGLE CHANNEL CONNECTIONIRC modules with protocol C37.94 and G.703 are designed for back-to-back communication connections, so the ring con-figuration shown in the previous figure does not apply. To establish inter-relay communication in more than two URs, youneed to have two channel IRC module and enable DIRECT I/O CHANNEL CROSSOVER function in all relays, as shown inthe next figure. This configuration can be expanded to 16 URs, and this configuration does not provide redundancy ringsince both channels are made into single ring by the channel crossover function. As per the figure Typical Pin Interconnec-tion between Two G.703 Interfaces later in this chapter, the clock is supplied typically by multiplexer (MUX) and all URs arein Loop Timing Mode. If there is no MUX, then UR1 and UR3 can be in Internal Timing Mode and UR2 and UR4 can be inLoop Timing Mode. That is, connected channels must have opposite timing modes.Figure 3–30: RING CONFIGURATION FOR C37.94 MODULE (CONCEPT ALSO APPLIES TO G.703)842006A2.CDRTxTxTxTxUR 1UR 2UR 3UR 4RxRxRxRxMUX842236A1.CDRTx2UR 1Rx2Tx2UR 2Rx2UR 3MUXTx1Rx1Tx1Rx1UR 4MUXMUXTx1Rx1Tx2Rx2MUXTx2MUXRx2MUXMUXTx1Rx1
