Chapter 1. Technical overview 29requests for cache lines go to the appropriate microprocessor bus and not all fourof them, thereby improving performance.The three scalability ports are each connected to the memory controller throughindividual scalability links with a maximum theoretical bidirectional data rate of10.24 GBps per port.IBM eX4 has two PCIe bridges and each are connected to a HSS-IB port of thememory controller with a maximum theoretical bidirectional data rate of 6 GBps.As shown in Figure 1-12 on page 28, PCIe bridge 1 supplies four of the sevenPCI Express x8 slots on four independent PCI Express buses. PCIe bridge 2supplies the other three PCI Express x8 slots plus the onboard SAS devices,including the optional ServeRAID-MR10k and a 4x external onboard SAS port.A separate Southbridge is connected to the Enterprise Southbridge Interface(ESI) port of the memory controller through a PCIe x4 link with a maximumtheoretical bidirectional data rate of 2 GBps. The Southbridge supplies all theother onboard PCI devices, such as the USB ports, onboard Ethernet and thestandard RSA II.1.6.1 Hurricane 4Hurricane 4 is the north bridge component of the IBM eX4 chipset designed forlatest Intel Core™ Architecture-based processors which feature a newarchitecture for the processor front-side bus. Hurricane 4 supports theprocessors in the Xeon 7000 family of processors, including those with codenames of Tigerton and Dunnington.Hurricane 4 is an enhanced memory controller with Level 4 (L4) scalabilitycache. Hurricane 4 contains processor scalability support for up to 16 socketsacross four NUMA nodes. Hurricane 4 provides the following features: Reduced local and remote latency compared to the X3 chipset in the x3950 Integrated memory controller, NUMA controller, two I/O channels and threescalability ports Local memory used for scalability L4 cache for a multinode environment Connectivity to high speed memory hub module, two PCIe bridges, and aSouthbridge Scalability to 16 socket SMP system providing industry leading performance Support for four front-side buses, one for each of the four Intel Xeon® MPprocessors
