200 IBM eX5 Implementation Guidefashion to provide a balanced system and populating all processors identically is alsorequired by VMware.Looking at Figure 5-16 as an example, Processor 0 has DIMMs populated, but no DIMMs arepopulated that are connected to Processor 1. In this case, Processor 0 has access tolow-latency local memory and high-memory bandwidth. However, Processor 1 has accessonly to remote or “far” memory. So, threads executing on Processor 1 have a longer latency toaccess memory as compared to threads on Processor 0. This result is due to the latencypenalty incurred to traverse the QPI links to access the data on the other processor’s memorycontroller. The bandwidth to remote memory is also limited by the capability of the QPI links.The latency to access remote memory is more than 50% higher than local memory access.For these reasons, we advise that you populate all of the processors with memory,remembering the necessary requirements to ensure optimal interleaving and HemisphereMode.Figure 5-16 Memory latency when not spreading DIMMs across both processors5.10.4 Memory mirroringMemory mirroring is supported using HX5 and MAX5. On the HX5, when enabled, the firstDIMM quadrant is duplicated onto the second DIMM quadrant for each processor. For adetailed understanding of memory mirroring, see “Memory mirroring” on page 28.This section contains DIMM placements for each solution.DIMM placement: HX5Table 5-17 on page 201 lists the DIMM installation sequence for memory-mirroring modewhen one processor is installed.QPI linksIntel Xeon 7500Processor 0DIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMBuffer Buffer Buffer BufferMemorycontrollerMemorycontrollerIntel Xeon 7500Processor 1DIMMDIMMDIMMDIMMBuffer Buffer Buffer BufferMemorycontrollerMemorycontrollerLOCALREMOTEImportant: If using memory mirroring, all DIMMs must be identical in size and rank.
