202 IBM eX5 Implementation Guide5.10.5 Memory sparingThe HX5 supports DIMM sparing, but only on the DIMMs that are installed in the HX5, not inthe MAX5. For more information about memory sparing, see “Memory sparing” on page 29.Table 5-20 shows the installation order when one processor is installed.Table 5-20 DIMM installation for the HX5 memory sparing: One processorTable 5-21 shows the installation order when two processors are installed.Table 5-21 DIMM installation for the HX5 memory sparing: Two processorsSparing: Rank sparing is not supported on the HX5. MAX5 does not support rank sparing or DIMM sparing. Rank sparing or DIMM sparingworks on an HX5 with a MAX5, but memory is only spared on the HX5.Number ofprocessorsNumber ofDIMMsProcessor 1 Processor 2Buffer Buffer Buffer Buffer Buffer Buffer Buffer BufferDIMM 1DIMM 2DIMM 3DIMM 4DIMM 5DIMM 6DIMM 7DIMM 8DIMM 9DIMM 10DIMM 11DIMM 12DIMM 13DIMM 14DIMM 15DIMM 161 4 x x x x1 8 x x x x x x x xNumber ofprocessorsNumber ofDIMMsProcessor 1 Processor 2Buffer Buffer Buffer Buffer Buffer Buffer Buffer BufferDIMM 1DIMM 2DIMM 3DIMM 4DIMM 5DIMM 6DIMM 7DIMM 8DIMM 9DIMM 10DIMM 11DIMM 12DIMM 13DIMM 14DIMM 15DIMM 162 4 x x x x2 8 x x x x x x x x2 12 x x x x x x x x x x x x2 16 x x x x x x x x x x x x x x x xRedundant bit steering: Redundant bit steering (RBS) is not supported on the HX5because the integrated memory controller of the Intel Xeon 7500 processors does notsupport the feature. See “Redundant bit steering” on page 29 for details.The MAX5 memory expansion blade supports RBS, but only with x4 memory and not x8memory. As shown in Table 5-13 on page 194, the 8 GB DIMM, part number 49Y1554,uses x4 DRAM technology. RBS is automatically enabled in the MAX5 memory port, if allDIMMs installed to that memory port are x4 DIMMs.
