30 IBM eX5 Implementation GuideRBS operates automatically without issuing a Predictive Failure Analysis (PFA) or light pathdiagnostics alert to the administrator, although an event is logged to the service processorlog. After the second DIMM failure, PFA and light path diagnostics alerts occur on that DIMMnormally.Lock stepIBM eX5 memory operates in lock step mode. Lock step is a memory protection feature thatinvolves the pairing of two memory DIMMs. The paired DIMMs can perform the sameoperations and the results are compared. If any discrepancies exist between the results, amemory error is signaled. Lock step mode gives a maximum of 64 GB of usable memory withone CPU installed, and 128 GB of usable memory with two CPUs installed (using 8 GBDIMMs).Memory must be installed in pairs of two identical DIMMs per processor. Although the size ofthe DIMM pairs installed can differ, the pairs must be of the same speed.Machine Check Architecture (MCA)MCA is a RAS feature that has previously only been available for other processorarchitectures, such as Intel Itanium®, IBM POWER®, and other reduced instruction setcomputing (RISC) processors, and mainframes. Implementation of the MCA requireshardware support, firmware support, such as the UEFI, and operating system support.The MCA enables system-error handling that otherwise requires stopping the operatingsystem. For example, if a memory location in a DIMM no longer functions properly and itcannot be recovered by the DIMM or memory controller logic, MCA logs the failure andprevents that memory location from being used. If the memory location was in use by a threadat the time, the process that owns the thread is terminated.Microsoft, Novell, Red Hat, VMware, and other operating system vendors have announcedsupport for the Intel MCA on the Xeon processors.Scalable memory buffersUnlike the Xeon 5500 and 5600 series, which use unbuffered memory channels, the Xeon6500 and 7500 processors use scalable memory buffers in the systems design. Thisapproach reflects the various workloads for which these processors were intended. The 6500and 7500 family processors are designed for workloads requiring more memory, such asvirtualization and databases. The use of scalable memory buffers allows more memory perprocessor, and prevents memory bandwidth reductions when more memory is added perprocessor.2.3.7 I/O hubsThe connection to I/O devices (such as keyboard, mouse, and USB) and to I/O adapters(such as hard disk drive controllers, Ethernet network interfaces, and Fibre Channel host busadapters) is handled by I/O hubs, which then connect to the processors through QPI links.Figure 2-4 on page 20 shows the I/O hub connectivity. Connections to the I/O devices arefault tolerant, because data can be routed over either of the two QPI links to each I/O hub. Foroptimal system performance in the four processor systems (with two I/O hubs), balance thehigh-throughput adapters across the I/O hubs.
