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NXP Semiconductors MPC5566 Reference Manual

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Contents
  1. MPC5566 Reference Manual,
  2. MPC5566 Reference Manual Addendum, Rev
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. Table Of Contents
  36. Table Of Contents
  37. Table Of Contents
  38. Table Of Contents
  39. Table Of Contents
  40. Table Of Contents
  41. Table Of Contents
  42. Table Of Contents
  43. Table Of Contents
  44. Table Of Contents
  45. Table Of Contents
  46. Table Of Contents
  47. MPC5566 Microcontroller Reference Manual, Rev
  48. Rev.
  50. Features
  51. MPC5500 Family Comparison
  52. Detailed Features
  53. System Bus Crossbar Switch (XBAR)
  54. Frequency Modulated Phase-Locking Loop (FMPLL)
  55. Cache
  56. Enhanced Management Input/Output System (eMIOS)
  57. Enhanced Serial Communications Interface (eSCI)
  58. Fast Ethernet Controller (FEC)
  59. MPC5500 Family Memory Map
  60. Multi-Master Operation Memory Map
  61. Block Diagram
  62. External Signal Descriptions
  63. Device Signals Summary
  64. Detailed Signal Description
  65. Reset and Configuration Signals
  66. RSTCFG_GPIO[210]
  67. External Address / Master Address Expansion / GPIO ADDR[30:31]_ADDR[6:7]_GPIO[26:27]
  68. DATA[22]_FEC_RXD[0]_GPIO[50]
  69. DATA[30]_FEC_RXD[2]_GPIO[58]
  70. TEA_FEC_RXD[3]_GPIO[71]
  71. MDO[0]
  72. JCOMP
  73. CNRXC_PCSD[4]_GPIO[88]
  74. SOUTA_PCSC[5]_GPIO[95]
  75. SCKB_PCSC[1]_GPIO[102]
  76. PCSB[4]_SCKC_GPIO[109]
  77. AN[5]_DAN2–
  78. AN[12]_MA[0]_SDS
  79. AN[16:39]
  80. ETPUA[0]_ETPUA[12]_GPIO[114]
  81. ETPUA[6]_ETPUA[18]_GPIO[120]
  82. ETPUA[13]_PCSB[3]_GPIO[127]
  83. ETPUA[21]_IRQ[9]_GPIO[135]
  84. TCRCLKB_IRQ[6]_GPIO[146]
  85. EMIOS[13]_SOUTD_GPIO[192]
  86. eMIOS Channel /eTPU B Output Channel / GPIO EMIOS[20:21]_ETPUB[4:5]_GPIO[199:200]
  87. Calibration Bus Signals
  88. CAL_TS
  89. VDDAn
  90. VDDEHn
  91. eTPU Pin Connections and Serialization
  92. ETPUA[16:31]
  93. ETPUB[0:31]
  94. eMIOS Pin Connections and Serialization
  95. Introduction
  97. Overview
  98. Instruction Unit Features
  99. MMU Features
  100. Core Registers and Programmer's Model
  101. Power Architecture Registers
  102. Supervisor-Level Only Registers
  103. Core-Specific Registers
  104. e200z6 Core Complex Features Not Supported in the Device
  105. Functional Description
  106. Translation Flow
  107. Effective to Real Address Translation
  108. MMU Assist Registers (MAS[0:4], MAS[6])
  109. MAS[1] Register
  110. MAS[2] Register
  111. MAS[3] Register
  112. MAS[6] Register
  113. L1 Cache
  114. Cache Organization
  115. Cache Line Replacement Algorithm
  116. L1 Cache Control and Status Register 0 (L1CSR0)
  117. L1 Cache Configuration Register 0 (L1CFG0)
  118. Interrupt Types
  119. Bus Interface Unit (BIU)
  120. Signal Processing Extension APU (SPE APU)
  121. External References
  123. External Signal Description
  124. Reset Configuration (RSTCFG)
  125. System Reset Control Register (SIU_SRCR)
  127. Reset Sources
  128. External Reset
  129. Loss-of-Clock Reset
  130. Checkstop Reset
  131. Software System Reset
  132. RSTCFG Pin
  133. PLLCFG[0:1] Pins
  134. Invalid RCHW
  135. Reset Configuration Timing
  136. Reset Flow
  140. Master Privilege Control Register (PBRIDGE_x_MPCR)
  141. ripheral Access Control Registers (PBRIDGE_x_OPACR)
  143. Read Cycles
  146. Detailed Signal Descriptions
  147. Reset Output (RSTOUT)
  148. I/O Weak Pullup Reset Configuration (WKPCFG)
  149. External Interrupts
  150. Edge-Detect Events
  151. Register Descriptions
  152. MCU ID Register (SIU_MIDR)
  153. Reset Status Register (SIU_RSR)
  155. External Interrupt Status Register (SIU_EISR)
  156. DMA Interrupt Request Enable Register (SIU_DIRER)
  157. DMA/Interrupt Request Select Register (SIU_DIRSR)
  158. Overrun Status Register (SIU_OSR)
  159. Overrun Request Enable Register (SIU_ORER)
  160. IRQ Rising-Edge Event Enable Register (SIU_IREER)
  161. IRQ Digital Filter Register (SIU_IDFR)
  162. Pad Configuration Registers (SIU_PCR)
  163. Pad Configuration Register 0 (SIU_PCR0)
  164. Pad Configuration Registers 1–3 (SIU_PCR1–SIU_PCR3)
  165. Pad Configuration Registers 4–7 (SIU_PCR4–SIU_PCR7)
  166. Pad Configuration Registers 23–25 (SIU_PCR23–SIU_PCR25)
  167. Pad Configuration Registers 26–27 (SIU_PCR26–SIU_PCR27)
  168. Pad Configuration Registers 44 (SIU_PCR44)
  169. Pad Configuration Registers 47 (SIU_PCR47)
  170. Pad Configuration Registers 49 (SIU_PCR49)
  171. Pad Configuration Registers 51 (SIU_PCR51)
  172. Pad Configuration Registers 52 (SIU_PCR52)
  173. Pad Configuration Registers 54 (SIU_PCR54)
  174. Pad Configuration Registers 55 (SIU_PCR55)
  175. Pad Configuration Registers 57 (SIU_PCR57)
  176. Pad Configuration Registers 58 (SIU_PCR58)
  177. Pad Configuration Registers 60–61 (SIU_PCR60–SIU_PCR61)
  178. Pad Configuration Register 62 (SIU_PCR62)
  179. Pad Configuration Registers 64–65 (SIU_PCR64–SIU_PCR65)
  180. Pad Configuration Register 68 (SIU_PCR68)
  181. Pad Configuration Register 70 (SIU_PCR70)
  182. Pad Configuration Register 72 (SIU_PCR72)
  183. Pad Configuration Register 73 (SIU_PCR73)
  184. Pad Configuration Register 82–75 (SIU_PCR82–SIU_PCR75)
  185. Pad Configuration Register 84 (SIU_PCR84)
  186. Pad Configuration Register 86 (SIU_PCR86)
  187. Pad Configuration Register 87 (SIU_PCR87)
  188. Pad Configuration Register 89 (SIU_PCR89)
  189. Pad Configuration Register 91 (SIU_PCR91)
  190. Pad Configuration Register 93 (SIU_PCR93)
  191. Pad Configuration Register 94 (SIU_PCR94)
  192. Pad Configuration Registers 96 (SIU_PCR96)
  193. Pad Configuration Registers 97 (SIU_PCR97)
  194. Pad Configuration Register 99 (SIU_PCR99)
  195. Pad Configuration Register 100 (SIU_PCR100)
  196. Pad Configuration Register 102 (SIU_PCR102)
  197. Pad Configuration Register 103 (SIU_PCR103)
  198. Pad Configuration Register 105 (SIU_PCR105)
  199. Pad Configuration Register 106 (SIU_PCR106)
  200. Pad Configuration Register 108 (SIU_PCR108)
  201. Pad Configuration Register 109 (SIU_PCR109)
  202. Pad Configuration Registers 111–112 (SIU_PCR111–SIU_PCR112)
  203. Pad Configuration Register 114–117 (SIU_PCR114–SIU_PCR117)
  204. Pad Configuration Register 118 (SIU_PCR118)
  205. Pad Configuration Register 120 (SIU_PCR120)
  206. Pad Configuration Register 121 (SIU_PCR121)
  207. Pad Configuration Registers 122–124 (SIU_PCR122–SIU_PCR124)
  208. Pad Configuration Register 126 (SIU_PCR126)
  209. Pad Configuration Registers 127–129 (SIU_PCR127–SIU_PCR129)
  210. Pad Configuration Register 134 (SIU_PCR134)
  211. Pad Configuration Register 135 (SIU_PCR135)
  212. Pad Configuration Register 137 (SIU_PCR137)
  213. Pad Configuration Registers 138–141 (SIU_PCR138–SIU_PCR141)
  214. Pad Configuration Register 145 (SIU_PCR145)
  215. Pad Configuration Registers 147–162 (SIU_PCR147–SIU_PCR162)
  216. Pad Configuration Registers 163 (SIU_PCR163–SIU_PCR166)
  217. Pad Configuration Registers 167–178 (SIU_PCR167–SIU_PCR178)
  218. Pad Configuration Register 189–190 (SIU_PCR189–SIU_PCR190)
  219. Pad Configuration Register 191 (SIU_PCR191)
  220. Pad Configuration Register 193 (SIU_PCR193)
  221. Pad Configuration Register 194 (SIU_PCR194)
  222. Pad Configuration Register 196 (SIU_PCR196)
  223. Pad Configuration Register 197 (SIU_PCR197)
  224. Pad Configuration Registers 199–200 (SIU_PCR199–SIU_PCR200)
  225. Pad Configuration Register 201 (SIU_PCR201)
  226. Pad Configuration Registers 203–204 (SIU_PCR203–SIU_PCR204)
  227. Pad Configuration Registers 206–207 (SIU_PCR206–SIU_PCR207)
  228. Pad Configuration Register 208 (SIU_PCR208)
  229. Pad Configuration Register 210 (SIU_PCR210)
  230. Pad Configuration Registers 211–212 (SIU_PCR211–SIU_PCR212)
  231. Pad Configuration Register 214 (SIU_PCR214)
  232. Pad Configuration Register 216 (SIU_PCR216)
  233. Pad Configuration Register 218 (SIU_PCR218)
  234. Pad Configuration Register 225–224 (SIU_PCR225–SIU_PCR224)
  235. Pad Configuration Register 229 (SIU_PCR229)
  236. Pad Configuration Registers 257–258 (SIU_PCR257–SIU_PCR258)
  237. Pad Configuration Register 261 (SIU_PCR261)
  238. Pad Configuration Register 262 (SIU_PCR262)
  239. Pad Configuration Register 265 (SIU_PCR265)
  240. Pad Configuration Register 267 (SIU_PCR267)
  241. Pad Configuration Registers 270–271 (SIU_PCR270–SIU_PCR271)
  242. Pad Configuration Register 275 (SIU_PCR275)
  243. Pad Configuration Register 278–293 (SIU_PCR278–SIU_PCR293)
  244. Pad Configuration Register 295–296 (SIU_PCR295–SIU_PCR296)
  245. Pad Configuration Register 299 (SIU_PCR299)
  246. GPIO Pin Data Input Registers 0–213 (SIU_GPDIn)
  247. eQADC Trigger Input Select Register (SIU_ETISR)
  248. External IRQ Input Select Register (SIU_EIISR)
  249. DSPI Input Select Register (SIU_DISR)
  250. Chip Configuration Register (SIU_CCR)
  251. External Clock Control Register (SIU_ECCR)
  252. Compare A Register High (SIU_CARH)
  253. Compare A Register Low (SIU_CARL)
  254. Compare B Register High (SIU_CBRH)
  255. Boot Configuration
  256. Reset Control
  257. GPIO Operation
  258. eQADC External Trigger Input Multiplexing
  259. SIU External Interrupt Input Multiplexing
  262. Modes of Operation
  264. Slave General-Purpose Control Registers (XBAR_SGPCRn)
  266. Master Ports
  267. Priority Assignment
  268. Parking
  270. Memory Map and Register Definition
  272. ECC Configuration Register (ECSM_ECR)
  273. ECC Error Generation Register (ECSM_EEGR)
  274. Flash ECC Address Register (ECSM_FEAR)
  275. Flash ECC Master Number Register (ECSM_FEMR)
  276. Flash ECC Data High Register (ECSM_FEDRH)
  277. Flash ECC Data Low Registers (ECSM_FEDRL)
  278. RAM ECC Address Register (ECSM_REAR)
  279. RAM ECC Master Number Register (ECSM_REMR)
  280. RAM ECC Data High Register (ECSM_REDRH)
  281. RAM ECC Data Low Registers (ECSM_REDRL)
  282. Initialization and Application Information
  288. eDMA Error Status Register (EDMA_ESR)
  289. eDMA Enable Request Registers (EDMA_ERQRH, EDMA_ERQRL)
  290. eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)
  291. eDMA Set Enable Request Register (EDMA_SERQR)
  292. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
  293. eDMA Clear Interrupt Request Register (EDMA_CIRQR)
  294. eDMA Set START Bit Register (EDMA_SSBR)
  295. eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)
  296. eDMA Error Registers (EDMA_ERH, EDMA_ERL)
  297. DMA Hardware Request Status (EDMA_HRSH, EDMA_HRSL)
  298. eDMA Channel n Priority Registers (EDMA_CPRn)
  299. Transfer Control Descriptor (TCD)
  301. eDMA Basic Data Flow
  302. eDMA Performance
  304. DMA Programming Errors
  305. DMA Request Assignments
  306. DMA Arbitration Mode Considerations
  307. Fixed-Group Arbitration, Round-Robin Channel Arbitration
  308. Multiple Requests
  309. Modulo Feature
  310. Active Channel TCD Reads
  311. Dynamic Programming
  316. Hardware Vector Mode
  320. INTC Current Priority Register (INTC_CPR)
  321. INTC End-of-Interrupt Register (INTC_EOIR)
  322. INTC Priority Select Registers (INTC_PSR0–329)
  324. Peripheral Interrupt Requests
  325. Unique Vector for Each Interrupt Request Source
  326. Vector Encoder Submodule
  327. Details on Handshaking with Processor
  328. Hardware Vector Mode Handshaking
  330. Software Vector Mode
  332. Order of Execution
  333. Priority Ceiling Protocol
  334. and Deadlines
  335. Scheduling an ISR on Another Processor
  336. Negating an Interrupt Request Outside of its ISR
  338. FMPLL and Clock Architecture
  339. FMPLL Bypass Mode
  340. FMPLL External Reference Mode
  341. FMPLL Crystal Reference Mode Without FM
  342. FMPLL Crystal Reference Mode With FM
  343. FMPLL Dual-Controller Mode (1:1)
  345. FMPLL Modes of Operation
  346. External Reference Mode
  347. Bypass Mode
  349. Synthesizer Status Register (FMPLL_SYNSR)
  351. Software Controlled Power Management/Clock Gating
  352. External Bus Clock (CLKOUT)
  353. Clock Operation
  354. FMPLL Loss-of-Lock Reset
  356. Programming System Clock Frequency Without Frequency Modulation
  357. Programming System Clock Frequency with Frequency Modulation
  358. FM Calibration Routine
  363. Module Disable Mode
  364. Debug Mode
  366. Burst Data in Progress (BDIP)
  367. Transfer Acknowledge (TA)
  368. Bus Busy (BB)
  369. Transfer Size 0 through 1 (TSIZ[0:1])
  370. Signal Function and Direction by Mode
  373. EBI Transfer Error Status Register (EBI_TESR)
  374. EBI Bus Monitor Control Register (EBI_BMCR)
  375. EBI Base Registers 0–3 (EBI_BRn and EBI Calibration Base Registers 0–3 (EBI_CAL_BRn)
  376. EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration Option Registers
  378. Memory Controller with Support for Various Memory Types
  379. Burst Support (Wrapped Only)
  380. Port Size Configuration per Chip Select (16 or 32 Bits)
  381. Configurable Bus Speed Clock Modes
  382. Misaligned Access Support
  383. External Bus Operations
  384. External Clocking
  385. Single-Beat Transfer
  386. Single-Beat Write Flow
  387. Back-to-Back Accesses
  388. Burst Transfer
  389. Small Access Example #3: 32-byte Read to 32-bit Port with
  390. TBDIP Effect on Burst Transfer
  391. Small Accesses (Small Port Size and Short Burst Length)
  392. Small Access Example #1: 32-bit Write to 16-bit Port
  393. Size, Alignment, and Packaging on Transfers
  394. Arbitration
  395. External (or Central) Bus Arbiter
  396. Internal Bus Arbiter
  397. Termination Signals Protocol
  398. Bus Operation in External Master Mode
  399. Address Decoding for External Master Accesses
  400. Bus Transfers Initiated by an External Master
  401. Bus Transfers Initiated by the EBI in External Master Mode
  402. Back-to-Back Transfers in External Master Mode
  403. Non-Chip-Select Burst in 16-bit Data Bus Mode
  404. Calibration Bus Operation
  406. Running with Asynchronous Memories
  407. Timing and Connections for Asynchronous Memories
  408. Connecting an MCU to Multiple Memories
  412. Flash Memory Map
  414. MCR Simultaneous Register Writes
  415. Low/Mid Address Space Block Locking Register (FLASH_LMLR)
  416. High Address Space Block Locking Register (FLASH_HLR)
  417. Low/Mid Address Space Block Select Register (FLASH_LMSR)
  418. High Address Space Block Select Register (FLASH_HSR)
  419. Flash Bus Interface Unit Control Register (FLASH_BIUCR)
  420. Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR)
  421. FBIU Basic Interface Protocol
  422. FBIU Line Read Buffers and Prefetch Operation
  423. FBIU Per-Master Prefetch Triggering
  424. Read While Write (RWW)
  425. Software Locking
  426. Flash Erase Suspend/Resume
  427. Flash Shadow Block
  428. Flash Disable
  429. FLASH_BIUAPR Modification
  430. Flash Memory Array: Reset
  432. Register Memory Map
  433. Access Timing
  434. Reset Effects on SRAM Accesses
  435. Example Code
  439. Interface Options
  440. Top Level Module Memory Map
  441. Registers
  442. FEC Registers
  443. Ethernet Interrupt Mask Register (EIMR)
  444. Receive Descriptor Active Register (RDAR)
  445. Transmit Descriptor Active Register (TDAR)
  446. Ethernet Control Register (ECR)
  447. MII Management Frame Register (MMFR)
  448. MII Speed Control Register (MSCR)
  449. MIB Control Register (MIBC)
  450. Receive Control Register (RCR)
  451. Transmit Control Register (TCR)
  452. Physical Address Low Register (PALR)
  453. Physical Address Upper Register (PAUR)
  454. Descriptor Individual Upper Address Register (IAUR)
  455. Descriptor Individual Lower Address (IALR)
  456. Descriptor Group Upper Address (GAUR)
  457. FIFO Transmit FIFO Watermark Register (TFWR)
  458. FIFO Receive Bound Register (FRBR)
  459. Receive Descriptor Ring Start (ERDSR)
  460. Transmit Buffer Descriptor Ring Start (ETDSR)
  461. Initialization Sequence
  462. Application Initialization (Prior to Asserting ECR[ETHER_EN])
  463. Microcontroller Initialization
  464. FEC Frame Transmission
  465. FEC Frame Reception
  466. Ethernet Address Recognition
  467. Hash Algorithm
  468. Full Duplex Flow Control
  469. Inter-Packet Gap (IPG) Time
  470. Ethernet Error-Handling Procedure
  471. Reception Errors
  472. Driver/DMA Operation with Transmit BDs
  473. Ethernet Receive Buffer Descriptor (RxBD)
  474. Ethernet Transmit Buffer Descriptor (TxBD)
  477. Serial Boot Mode
  478. BAM Program Operation
  479. Internal Boot Mode
  480. External Boot Modes
  481. Single Bus Master or Multiple Bus Masters
  482. Read the Reset Configuration Halfword
  483. Serial Boot Mode FlexCAN and eSCI Configuration
  484. Download Process for FlexCAN Serial Boot Mode
  485. eSCI Serial Boot Mode Download Process
  486. Interrupts
  489. eMIOS Operating Modes
  491. Output Disable Input—eMIOS Output Disable Input Signals
  492. Register Description
  493. eMIOS Global Flag Register (EMIOS_GFR)
  494. eMIOS Output Update Disable Register (EMIOS_OUDR)
  495. eMIOS Channel A Data Register (EMIOS_CADRn)
  496. eMIOS Channel Counter Register (EMIOS_CCNTRn)
  497. eMIOS Channel Status Register (EMIOS_CSRn)
  498. eMIOS Alternate Address Register (EMIOS_ALTAn)
  500. Effect of Freeze on the STAC Client Submodule
  501. Unified Channel (UC)
  502. Programmable Input Filter (PIF)
  503. Clock Prescaler (CP)
  504. General Purpose Input/Output Mode (GPIO)
  505. Single-action Output Compare Mode (SAOC)
  506. Input Pulse-Width Measurement Mode (IPWM)
  507. Input Period Measurement Mode (IPM)
  508. Double-action Output Compare Mode (DAOC)
  509. Pulse/Edge Accumulation Mode (PEA)
  510. Pulse and Edge Counting Mode (PEC)
  511. Quadrature Decode Mode (QDEC)
  512. Windowed Programmable Time Accumulation Mode (WPTA)
  513. Modulus Counter Mode (MC)
  514. Output Pulse-Width Modulation Mode (OPWM)
  515. Modulus Counter Buffered Mode (MCB)
  516. Output Pulse-Width Modulation, Buffered Mode (OPWMB)
  517. Initialization/Application Information
  520. eTPU Operation Overview
  521. eTPU Engine
  522. eTPU Timer Channels
  523. Shared Data Memory (SDM)
  524. Task Scheduler
  525. Microengine
  527. User Configuration Mode
  528. Output and Input Channel Signals
  529. Time Base Clock Signal (TCRCLKA and TCRCLKB)
  531. eTPU Register Addresses
  532. System Configuration Registers
  533. eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR)
  534. eTPU MISC Compare Register (ETPU_MISCCMPR)
  535. eTPU Engine Configuration Register (ETPU_ECR)
  536. Time Base Registers
  537. eTPU Time Base Configuration Register (ETPU_TBCR)
  538. eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)
  539. eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
  540. STAC Bus Configuration Register (ETPU_REDCR)
  541. Global Channel Registers
  542. eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
  543. eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)
  544. eTPU Channel Interrupt Enable Register (ETPU_CIER)
  545. eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)
  546. eTPU Channel Pending Service Status Register (ETPU_CPSSR)
  547. eTPU Channel Service Status Register (ETPU_CSSR)
  548. Channel Registers Layout
  549. eTPU Channel n Configuration Register (ETPU_CnCR)
  550. eTPU Channel n Status Control Register (ETPU_CnSCR)
  551. eTPU Channel n Host Service Request Register (ETPU_CnHSRR)
  557. Stop Mode
  560. eQADC Register Descriptions
  561. eQADC Null Message Send Format Register (EQADC_NMSFR)
  562. eQADC External Trigger Digital Filter Register (EQADC_ETDFR)
  563. eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn)
  564. eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn)
  565. eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn)
  566. eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)
  567. eQADC CFIFO Transfer Counter Registers 0–5 (EQADC_CFTCRn)
  568. eQADC CFIFO Status Register (EQADC_CFSR)
  569. eQADC SSI Control Register (EQADC_SSICR)
  570. eQADC SSI Receive Data Register (EQADC_SSIRDR)
  571. eQADC CFIFO Registers (EQADC_CF[0–5]Rn)
  572. eQADC RFIFO Registers (EQADC_RF[0–5]Rn)
  573. On-Chip ADC Registers
  574. ADCn Control Registers (ADC0_CR and ADC1_CR)
  575. ADC Time Stamp Control Register (ADC_TSCR)
  576. ADC Time Base Counter Registers (ADC_TBCR)
  578. Data Flow in the eQADC
  579. Assumptions/Requirements Regarding the External Device
  580. Command Execution and Result Return
  581. Message Formats for On-Chip ADC Operation
  582. Message Formats for External Device Operation
  583. Command/Result Queues
  584. CFIFO Prioritization and Command Transfer
  585. External Trigger from eTPU or eMIOS Channels
  586. CFIFO Scan Trigger Modes
  587. Single-Scan Mode
  588. Continuous-Scan Mode
  589. CFIFO Scan Trigger Mode Start/Stop Summary
  590. CFIFO and Trigger Status
  591. Command Queue Completion Status
  592. Pause Status
  593. Trigger Overrun Status
  594. Result FIFOs
  595. Distributing Result Data into RFIFOs
  596. On-Chip ADC Configuration and Control
  597. Time Stamp Feature
  598. MAC Unit and Operand Data Format
  599. ADC Control Logic Overview and Command Execution
  600. Internal/External Multiplexing
  601. External Multiplexing
  602. eQADC eDMA/Interrupt Request
  603. eQADC Synchronous Serial Interface (SSI) Submodule
  604. eQADC SSI Data Transmission Protocol
  605. Abort Feature
  606. Analog Submodule
  607. RSD Overview
  608. RSD Adder
  609. Initialization of On-Chip ADCs and an External Device
  610. Configuring eQADC for Applications
  611. eQADC/eDMA Controller Interface
  612. Receive Queue/RFIFO Transfers
  613. Sending Immediate Command Setup Example
  614. Command Queue and Result Queue Usage
  615. ADC Result Calibration
  616. MAC Configuration Procedure
  617. Example Calculation of Calibration Constants
  618. eQADC versus QADC
  624. Peripheral Chip Select 4 / Master Trigger (PCSx[4]_MTRIG)
  626. DSPI Transfer Count Register (DSPIx_TCR)
  627. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
  628. DSPI Status Register (DSPIx_SR)
  629. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
  630. DSPI POP RX FIFO Register (DSPIx_POPR)
  631. DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn)
  632. DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn)
  633. DSPI DSI Configuration Register (DSPIx_DSICR)
  634. DSPI DSI Serialization Data Register (DSPIx_SDR)
  635. DSPI DSI Alternate Serialization Data Register (DSPIx_ASDR)
  636. DSPI DSI Transmit Comparison Register (DSPIx_COMPR)
  637. DSPI DSI Deserialization Data Register (DSPIx_DDR)
  639. Master Mode
  641. Serial Peripheral Interface (SPI) Configuration
  642. FIFO Disable Operation
  643. Draining the TX FIFO
  644. Draining the RX FIFO
  645. DSI Slave Mode
  646. DSI Deserialization
  647. Change In Data Control
  648. DSPI B Connectivity
  649. DSPI C Connectivity
  650. DSPI D Connectivity
  651. Multiple Transfer Operation (MTO)
  652. Internal Muxing and SIU Support for Serial and Parallel Chaining
  653. Parallel Chaining
  654. Serial Chaining
  655. Combined Serial Interface (CSI) Configuration
  656. CSI Deserialization
  657. DSPI Baud Rate and Clock Delay Generation
  658. Peripheral Chip Select Strobe Enable (PCSS)
  659. Transfer Formats
  660. Classic SPI Transfer Format (CPHA = 0)
  661. Classic SPI Transfer Format (CPHA = 1)
  662. Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Cleared (CPHA = 0) for SPI and DSI
  663. Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Set (CPHA = 1) for SPI and DSI
  664. Continuous Selection Format
  665. Clock Polarity Switching between DSPI Transfers
  666. Interrupts and DMA Requests
  667. Transmit FIFO Underflow Interrupt Request (TFUF)
  668. Slave Interface Signal Gating
  669. Baud Rate Settings
  670. Delay Settings
  671. Calculation of FIFO Pointer Addresses
  672. Entry in the TX FIFO
  677. eSCI Control Register 2 (ESCIx_CR2)
  678. eSCI Data Register (ESCIx_DR)
  679. eSCI Status Register (ESCIx_SR)
  680. LIN Control Register (ESCIx_LCR)
  681. LIN Transmit Register (ESCIx_LTR)
  682. LIN Receive Register (ESCIx_LRR)
  683. LIN CRC Polynomial Register (ESCIx_LPR)
  685. Data Format
  686. Baud Rate Generation
  687. Transmitter
  688. Break Characters
  689. Fast Bit Error Detection in LIN Mode
  690. Receiver
  691. Character Reception
  692. Framing Errors
  693. Slow Data Tolerance
  694. Fast Data Tolerance
  695. Idle Input Line Wake-up (WAKE = 0)
  696. Loop Operation
  697. Disabling the eSCI
  698. Features of the LIN Hardware
  699. Generating an RX Frame
  700. LIN Error Handling
  701. LIN Setup
  707. Memory Map
  708. Message Buffer Structure
  710. Module Configuration Register (CANx_MCR)
  711. Control Register (CANx_CR)
  712. Free Running Timer (CANx_TIMER)
  713. RX Global Mask (CANx_RXGMASK)
  714. RX 14 Mask (CANx_RX14MASK)
  715. Error Counter Register (CANx_ECR)
  716. Error and Status Register (CANx_ESR)
  717. Interrupt Masks High Register (ICANx_IMRH)
  718. Interrupt Flags High Register (CANx_IFRH)
  719. Interrupt Flags Low Register (CANx_IFRL)
  720. Transmit Process
  721. Receive Process
  722. Reception Queue
  723. Notes on TX Message Buffer Deactivation
  724. CAN Protocol Related Features
  725. Time Stamp
  726. Arbitration and Matching Timing
  727. Module Disabled Mode
  728. Bus Interface
  729. FlexCAN2 Addressing and RAM Size
  732. POR Circuits
  733. V POR Circuit
  734. Compatible Power Transistors
  735. Pin Values after POR Negates
  738. IEEE 1149.1-2001 Defined Test Modes
  740. Bypass Register
  742. Enabling the TAP Controller
  743. BYPASS Instruction
  744. HIGHZ Instruction
  749. Reduced-Port Mode
  751. Test Data Input (TDI)
  752. NDI Functional Description
  753. Configuring the NDI for Nexus Messaging
  754. Programmable MCKO Frequency
  755. Nexus Port Controller (NPC)
  757. Port Configuration Register (PCR)
  758. NPC Functional Description
  759. Output Messages
  760. Rules of Messages
  761. Enabling the NPC TAP Controller
  762. Retrieving Device IDCODE
  763. Selecting a Nexus Client Register
  764. Nexus Auxiliary Port Sharing
  765. Nexus Reset Control
  766. e200z6 Class 3 Nexus Module (NZ6C3)
  769. Enabling Nexus3 Operation
  770. TCODEs Supported by NZ6C3
  771. NZ6C3 Memory Map and Register Definition
  773. Development Control Registers 1 and 2 (DC1, DC2)
  774. Development Status Register (DS)
  775. Read/Write Access Control and Status (RWCS)
  776. Read/Write Access Address (RWA)
  777. Watchpoint Trigger Register (WT)
  778. Data Trace Control Register (DTC)
  779. Data Trace Start Address Registers 1 and 2 (DTSAn)
  780. NZ6C3 Register Access via JTAG / OnCE
  781. Ownership Trace
  782. OTM Error Messages
  783. Branch Trace Messaging (BTM)
  784. BTM Using Branch History Messages
  785. BTM Message Formats
  786. Resource Full Messages
  787. Program Correlation Messages
  788. Program Trace Synchronization Messages
  789. BTM Operation
  790. Sequential Instruction Count (I-CNT)
  791. Data Trace
  792. Data Trace Messaging (DTM)
  793. DTM Overflow Error Messages
  794. DTM Operation
  795. Data Trace Timing Diagrams (Eight MDO Configuration)
  796. Watchpoint Support
  797. Watchpoint Error Message
  798. Watchpoint Timing Diagram (2 MDO and 1 MSEO Configuration)
  799. Single Write Access
  800. Block Write Access (Burst Mode)
  801. Block Read Access (Non-Burst Mode)
  802. Error Handling
  803. Examples
  804. IEEE‚ 1149.1 (JTAG) RD/WR Sequences
  805. JTAG Sequence for Read Access of Memory-Mapped Resources
  806. Nexus Crossbar eDMA Interface (NXDM)
  808. NXDM Nexus Register Map
  809. Development Control Registers (DC1 and DC2)
  811. Data Trace Start Address Registers 1 and 2 (DTSA1 and DTSA2)
  812. Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
  813. Breakpoint / Watchpoint Control Register 2 (BWC2)
  814. Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2)
  815. NXDM JTAG DID Register
  817. TCODEs Supported by NXDM
  819. Data Trace Synchronization Messages
  821. DTM Queueing
  822. Watchpoint Messaging
  823. A.1 Base Addresses of the Device Modules
  824. A.2 MPC5566 Register Map
  825. B.1 Overview
  826. B.2 Calibration Bus
  827. B.3 Device-Specific Information
  828. B.4.3 CLKOUT
  829. B.8 Application Information
  830. C.1 Changes Between Revisions 1 and 2
NXP Semiconductors MPC5566 Reference Manual Manual pdf 1 page image
© Freescale Semiconductor, Inc., 2012. All rights reserved.Freescale Semiconductor MPC5566RMRev. 2.1, 05/2012This MPC5566 Reference Manual set consists of the following files:• MPC5566 Reference Manual Addendum, Rev 2• MPC5566 Microcontroller Reference Manual, Rev 2MPC5566 MicrocontrollerReference Manual
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