NXP Semiconductors MC9S08SU16 Reference Manual Manual pdf 1 page image
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NXP Semiconductors MC9S08SU16 Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Overview
  31. Typographic notation
  32. Introduction
  33. S08L core modules
  34. Memories and memory interfaces
  35. Security and integrity modules
  36. Communication interfaces
  37. Human-machine interfaces
  38. Orderable part numbers
  39. Memory map
  40. Reset and interrupt vector assignments
  41. Register addresses assignments
  42. Random-access memory (RAM)
  43. System register file
  44. Interrupts
  45. Interrupt stack frame
  46. Hardware nested interrupt
  47. Interrupt priority level register
  48. Integration and application of the IPC
  49. IPC memory map and register descriptions
  50. Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
  51. Interrupt Level Setting Registers n (IPC_ILRSn)
  52. Features
  53. Configuration options
  54. Clock module
  55. Internal clock source (ICS)
  56. kHz low-power oscillator (LPO)
  58. Wait mode
  59. Power modes behaviors
  60. Bandgap reference
  62. Pinout
  63. Signal description table
  66. Port data and data direction
  67. Input glitch filter
  68. Memory map and register definition
  69. Port B Data Register (PORT_PTBD)
  70. Port A Direction Register (PORT_PTADD)
  71. Port B Direction Register (PORT_PTBDD)
  72. Port A Pullup Enable Register (PORT_PTAPE)
  73. Port B Pullup/Pulldown Enable Register (PORT_PTBPE)
  74. Port B High Drive Strength Selection Register (PORT_PTBHD)
  75. Port Filter Register 0 (PORT_IOFLT0)
  76. Port Filter Register 1 (PORT_IOFLT1)
  77. Port Filter Register 2 (PORT_IOFLT2)
  78. Chip specific windowed COP
  79. System device identification (SDID)
  80. Computer operating properly (COP) watchdog
  81. System options
  82. RESET_b pin enable
  83. Module to module interconnects
  85. System Reset Status Register (SIM_SRS)
  86. System Background Debug Force Reset Register (SIM_SBDFR)
  87. System Device Identification Register: Low (SIM_SDIDL)
  88. System Options Register 2 (SIM_SOPT2)
  89. System Port A Pin Multiplexing Control Register: Low (SIM_MUXPTAL)
  90. System Port A Pin Multiplexing Control Register: High (SIM_MUXPTAH)
  91. System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)
  92. System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH)
  93. System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)
  94. System Clock Gating Control 2 Register (SIM_SCGC2)
  95. System Clock Gating Control 3 Register (SIM_SCGC3)
  96. System Clock Divider Register (SIM_SCDIV)
  97. System POR Register (SIM_PORREGn)
  98. Illegal Address Register: High (SIM_ILLAH)
  99. Universally Unique Identifier Register 0 (SIM_UUID0)
  100. Universally Unique Identifier Register 2 (SIM_UUID2)
  101. Universally Unique Identifier Register 4 (SIM_UUID4)
  102. Universally Unique Identifier Register 6 (SIM_UUID6)
  104. Programmer's Model and CPU Registers
  105. Index Register (H:X)
  106. Program Counter (PC)
  107. Addressing Modes
  108. Inherent Addressing Mode (INH)
  109. Direct Addressing Mode (DIR)
  110. Indexed Addressing Mode
  111. Indexed, 8-Bit Offset with Post Increment (IX1+)
  112. SP-Relative, 16-Bit Offset (SP2)
  113. Indexed to Direct, Post Increment
  115. Security mode
  116. HCS08 V6 Opcodes
  117. Instruction Set Summary
  119. Other flash module features
  120. Flash memory map
  121. Writing the FCLKDIV register
  122. Command write sequence
  123. Flash interrupts
  124. Protection
  125. Security
  126. Unsecuring the MCU using backdoor key access
  127. Unsecuring the MCU using BDM
  128. Flash command summary
  129. Erase Verify All Blocks command
  130. Erase Verify Flash Section command
  131. Read once command
  132. Program Flash command
  133. Program Once command
  134. Erase All Blocks command
  135. Erase flash block command
  136. Unsecure flash command
  137. Verify backdoor access key command
  138. Set user margin level command
  139. Set factory margin level command
  141. Flash Clock Divider Register (FTMRH_FCLKDIV)
  142. Flash Security Register (FTMRH_FSEC)
  143. Flash CCOB Index Register (FTMRH_FCCOBIX)
  144. Flash Status Register (FTMRH_FSTAT)
  145. Flash Protection Register (FTMRH_FPROT)
  146. Flash Common Command Object Register:High (FTMRH_FCCOBHI)
  147. Flash Common Command Object Register: Low (FTMRH_FCCOBLO)
  149. Block diagram
  150. FLL bypassed internal (FBI)
  151. Register definition
  152. ICS Control Register 2 (ICS_C2)
  153. ICS Control Register 3 (ICS_C3)
  154. ICS Control Register 4 (ICS_C4)
  155. ICS Status Register (ICS_S)
  156. Functional description
  157. FLL engaged external (FEE)
  158. FLL bypassed external (FBE)
  159. Mode switching
  160. Fixed frequency clock
  161. External reference clock monitor
  162. Initializing FEE mode
  163. Chip specific modulo timer
  165. Modes of Operation
  166. MTIM16 in Active Background Mode
  167. Memory Map and Register Descriptions
  168. MTIM16 clock configuration register (MTIM_CLK)
  169. MTIM16 counter register high (MTIM_CNTH)
  170. MTIM16 counter register low (MTIM_CNTL)
  171. MTIM16 modulo register high (MTIM_MODH)
  172. MTIM16 modulo register low (MTIM_MODL)
  173. MTIM16 Operation Example
  174. Chip specific power management controller
  177. Full performance mode
  178. VDDF
  179. Control Register (PMC_CTRL)
  180. Reset Flags Register (PMC_RST)
  181. Temperature Offset Step Trim Register (PMC_TPTM)
  182. RC Oscillator Offset Step Trim Register (PMC_RC20KTRM)
  183. Low Voltage Control and Status Register 1 (system 5 V) (PMC_LVCTLSTAT1)
  184. VREFH Low Voltage Warning (LVW) Configuration Register (PMC_VREFHLVW)
  186. VREGVDD
  187. LVR in low power mode
  188. High-accuracy reference voltage
  189. Low-power RC oscillator
  190. Chip specific KBI information
  191. KBI in Wait mode
  192. External signals description
  193. KBI Status and Control Register (KBI_SC)
  194. KBI Pin Enable Register (KBI_PE)
  196. KBI Pullup Resistor
  197. Chip specific cyclic redundancy check (CRC)
  199. Run mode
  200. CRC Data register: High 0 (CRC_DH0)
  201. CRC Data register: Low 1 (CRC_DL1)
  202. CRC Polynomial Register: High 1 (CRC_PH1)
  203. CRC Polynomial Register: High 0 (CRC_PH0)
  204. CRC Polynomial Register: Low 0 (CRC_PL0)
  206. CRC calculations
  207. Transpose feature
  208. CRC result complement
  209. Chip-specific ADC information
  210. ADC channel assignments
  211. ADC analog supply and reference connections
  212. Hardware trigger
  215. Analog Channel Inputs (ADx)
  216. Status and Control Register 2 (ADCx_SC2)
  217. Status and Control Register 3 (ADCx_SC3)
  218. Status and Control Register 4 (ADCx_SC4)
  219. Conversion Result High Register (ADCx_RH)
  220. Conversion Result Low Register (ADCx_RL)
  221. Compare Value High Register (ADCx_CVH)
  224. Completing conversions
  225. Power control
  226. Automatic compare function
  227. FIFO operation
  228. MCU wait mode operation
  229. Initialization information
  230. Pseudo-code example
  232. Application information
  233. Analog input pins
  234. Sources of error
  235. Code width and quantization error
  236. Linearity errors
  237. Code jitter, non-monotonicity, and missing codes
  238. CMP configuration information
  239. ACMP in stop mode
  240. CMP Features
  241. ANMUX Key Features
  242. CMP Block Diagram
  243. Memory Map/Register Definitions
  244. CMP Control Register 1 (CMP_CR1)
  245. CMP Filter Period Register (CMP_FPR)
  246. CMP Status and Control Register (CMP_SCR)
  247. DAC Control Register (CMP_DACCR)
  248. MUX Control Register (CMP_MUXCR)
  249. MUX Pin Enable Register (CMP_MUXPE)
  250. CMP Functional Modes
  251. Disabled Mode (# 1)
  252. Sampled, Non-Filtered Mode (#s 3A & 3B)
  253. Sampled, Filtered Mode (#s 4A & 4B)
  254. Windowed Mode (#s 5A & 5B)
  255. Windowed/Resampled Mode (# 6)
  256. Windowed/Filtered Mode (#7)
  257. Stop Mode Operation
  258. Low Pass Filter
  259. Latency Issues
  260. CMP Interrupts
  261. DAC Functional Description
  262. Chip specific FlexTimer module
  265. Signal description
  266. EXTCLK — FTM external clock
  267. Status and Control (FTMx_SC)
  268. Counter High (FTMx_CNTH)
  269. Counter Low (FTMx_CNTL)
  270. Modulo Low (FTMx_MODL)
  271. Channel Status and Control (FTMx_CnSC)
  272. Channel Value High (FTMx_CnVH)
  273. Channel Value Low (FTMx_CnVL)
  275. Prescaler
  276. Up counting
  277. Free running counter
  278. Output compare mode
  279. Edge-aligned PWM (EPWM) mode
  280. Center-aligned PWM (CPWM) mode
  281. Update of the registers with write buffers
  282. CnVH:L registers
  283. FTM Interrupts
  284. Chip specific pules width timer
  287. PWTIN[3:0] — pulse width timer capture inputs
  288. Pulse Width Timer Control and Status Register (PWTx_CS)
  289. Pulse Width Timer Control Register (PWTx_CR)
  290. Pulse Width Timer Positive Pulse Width Register: High (PWTx_PPH)
  291. Pulse Width Timer Positive Pulse Width Register: Loq (PWTx_PPL)
  292. Pulse Width Timer Negative Pulse Width Register: Low (PWTx_NPL)
  294. Reset overview
  296. Application examples
  297. Initialization/Application information
  298. Chip specific inter-integrated circuit
  301. I2C signal descriptions
  302. I2C Address Register 1 (I2C_A1)
  303. I2C Control Register 1 (I2C_C1)
  304. I2C Status register (I2C_S)
  305. I2C Data I/O register (I2C_D)
  306. I2C Control Register 2 (I2C_C2)
  307. I2C Stop Control and Status Register (I2C_SCS)
  308. I2C Range Address register (I2C_RA)
  309. I2C SMBus Control and Status register (I2C_SMB)
  310. I2C Address Register 2 (I2C_A2)
  311. I2C SCL Low Timeout Register High (I2C_SLTH)
  312. I2C Status register 2 (I2C_S2)
  313. I2C protocol
  314. Slave address transmission
  315. STOP signal
  316. Clock synchronization
  317. Clock stretching
  318. bit address
  319. Master-receiver addresses a slave-transmitter
  320. System management bus specification
  321. FAST ACK and NACK
  322. Resets
  323. Byte transfer interrupt
  324. Timeout interrupt in SMBus
  325. Double buffering mode
  327. Chip specific serial communications interface
  330. SCI signal descriptions
  331. SCI Baud Rate Register: High (SCIx_BDH)
  332. SCI Baud Rate Register: Low (SCIx_BDL)
  333. SCI Control Register 2 (SCIx_C2)
  334. SCI Status Register 1 (SCIx_S1)
  335. SCI Status Register 2 (SCIx_S2)
  336. SCI Control Register 3 (SCIx_C3)
  337. SCI Data Register (SCIx_D)
  338. Baud rate generation
  339. Send break and queued idle
  340. Receiver functional description
  341. Data sampling technique
  342. Receiver wake-up operation
  343. Interrupts and status flags
  344. Baud rate tolerance
  345. Slow data tolerance
  346. Fast data tolerance
  347. Additional SCI functions
  348. Loop mode
  349. Chip specific programmable delay block
  351. Mode of operation
  352. Continuous count mode
  354. PDB Control Register 1 (PDB_CTRL1)
  355. PDB0 Comparison Low Register (PDB_CMPL0)
  356. PDB0 Comparison High Register (PDB_CMPH0)
  357. PDB1 Comparison Low Register (PDB_CMPL1)
  358. PDB1 Counter High/Low (PDB_CNT1)
  361. External Mux Selection Register (XBAR_EXTMUX)
  362. XBAR Selection Register (XBAR_SELn)
  363. Chip specific GDU information
  367. PHCMP0 Control Register 0 (GDU_PHCMP0CR0)
  368. PHCMP0 Filter Period Register (GDU_PHCMP0FPR)
  369. PHCMP1 Control Register 0 (GDU_PHCMP1CR0)
  370. PHCMP1 Control Register 1 (GDU_PHCMP1CR1)
  371. PHCMP1 Filter Period Register (GDU_PHCMP1FPR)
  372. PHCMP1 Status and Control Register (GDU_PHCMP1SCR)
  373. PHCMP2 Control Register 0 (GDU_PHCMP2CR0)
  374. PHCMP2 Filter Period Register (GDU_PHCMP2FPR)
  375. Clamp Control Register (GDU_CLMPCTRL)
  376. I/O Control Register (GDU_IOCTRL)
  377. Virtual Network Phase Detection Control (GDU_PHASECTRL)
  378. Current Sensor and Overcurrent Protection Control Register (GDU_CURCTRL)
  379. LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)
  380. LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)
  381. LIMIT0 CMP Status and Control Register (GDU_LIMIT0SCR)
  382. LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)
  383. LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)
  384. LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR)
  385. LIMIT1 CMP Status and Control Register (GDU_LIMIT1SCR)
  386. LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)
  387. LIMIT CMP BIAS Register (GDU_SIGBIAS)
  388. Phase detection function descriptions
  389. OpAMP function descriptions
  390. OpAMP descriptions
  391. Predrive descriptions
  392. GCMP diagram
  393. GCMP functional modes
  394. Power modes
  395. Startup and operation
  396. GCMP interrupts
  397. Chip specific pulse width modulator
  398. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors
  401. Alignment and compare output polarity
  402. Period
  403. Independent or complementary channel operation
  404. Deadtime generators
  405. Asymmetric PWM output
  406. PWM output polarity
  407. Generator loading
  408. Reload flag
  409. Initialization
  410. Fault protection
  411. Fault pin filter
  412. Automatic fault clearing
  414. PWM Control Register: Low (PWM_CTRLL)
  415. PWM Control Register: High (PWM_CTRLH)
  416. PWM Fault Control Register: Low (PWM_FCTRLL)
  417. PWM Fault Control Register: High (PWM_FCTRLH)
  418. PWM Fault Status Acknowledge Register: High (PWM_FLTACKH)
  419. PWM Output Control Register: Low (PWM_OUTL)
  420. PWM Output Control Register: High (PWM_OUTH)
  421. PWM Counter Register: High (PWM_CNTRH)
  422. PWM Counter Register: High (PWM_CMODH)
  423. PWM Value Register: High (PWM_VALnH)
  424. PWM Deadtime Register: Low (PWM_DTIMnL)
  425. PWM Disable Mapping Registers 1: Low (PWM_DMAP1L)
  426. PWM Disable Mapping Registers 1: High (PWM_DMAP1H)
  427. PWM Configure Register: High (PWM_CNFGH)
  428. PWM Channel Control Register: Low (PWM_CCTRLL)
  429. PWM Channel Control Register: High (PWM_CCTRLH)
  430. PWM Compare Invert Register: High (PWM_CINVH)
  434. Background debug controller (BDC)
  435. BKGD pin description
  436. Communication details
  437. BDC commands
  438. BDC hardware breakpoint
  439. Comparators A and B
  440. Bus capture information and FIFO operation
  441. Change-of-flow information
  442. Trigger modes
  443. Hardware breakpoints
  444. Memory map and register description
  445. BDC Breakpoint Match Register: High (BDC_BKPTH)
  446. BDC Breakpoint Register: Low (BDC_BKPTL)
  450. Debug Comparator A High Register (DBG_CAH)
  451. Debug Comparator A Low Register (DBG_CAL)
  452. Debug Comparator B High Register (DBG_CBH)
  453. Debug Comparator C High Register (DBG_CCH)
  454. Debug Comparator C Low Register (DBG_CCL)
  455. Debug FIFO Low Register (DBG_FL)
  456. Debug Comparator A Extension Register (DBG_CAX)
  457. Debug Comparator B Extension Register (DBG_CBX)
  458. Debug Comparator C Extension Register (DBG_CCX)
  459. Debug FIFO Extended Information Register (DBG_FX)
  460. Debug Trigger Register (DBG_T)
  461. Debug Status Register (DBG_S)
  462. Debug Count Status Register (DBG_CNT)
  464. Breakpoints
  465. Trigger selection
  466. Begin- and end-trigger
  468. FIFO
  469. Storing data in FIFO
  470. Interrupt priority
NXP Semiconductors MC9S08SU16 Reference Manual Manual pdf 1 page image
MC9S08SU16 Reference ManualSupports: MC9S08SU16VFK MC9S08SU8VFKDocument Number: MC9S08SU16RMRev. 5, 4/2017
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