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NXP Semiconductors MPC5606S Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. Table Of Contents
  36. Table Of Contents
  37. Table Of Contents
  38. Table Of Contents
  39. Introduction
  40. MPC5606S family comparison
  41. Block diagram
  42. Feature details
  43. e200z0h core processor
  44. Crossbar switch (XBAR)
  45. Enhanced Direct Memory Access (eDMA)
  46. Interrupt Controller (INTC)
  47. System Integration Unit (SIU)
  48. SRAM
  49. Enhanced Modular Input/Output System (eMIOS)
  50. Analog-to-Digital Converter (ADC)
  51. Deserial Serial Peripheral Interface (DSPI)
  52. FlexCAN
  53. Serial communication interface module (LINFlex)
  54. Periodic Interrupt Timer module (PIT)
  55. Real Time Counter (RTC)
  56. Parallel Data Interface (PDI)
  57. Liquid Crystal Display (LCD) driver
  58. Stepper Motor Controller (SMC)
  59. IEEE 1149.1 JTAG Controller (JTAGC)
  60. How to use the MPC5606S documents
  61. Using the MPC5606S
  62. Software design
  63. Input/output pins
  64. Chapter 2
  65. Memory Map
  71. Package pinouts
  72. Pad configuration during reset phases
  73. Pad types
  74. System pins
  75. Functional ports
  76. Signal details
  77. Register protection
  78. Modes of operation
  80. Register description
  81. Functional description
  82. Access errors
  83. Features
  84. External signal description
  86. SWT Interrupt Register (SWT_IR)
  87. SWT Timeout Register (SWT_TO)
  88. SWT Window Register (SWT_WN)
  89. SWT Counter Output Register (SWT_CO)
  91. Overview
  92. Device-specific implementation
  94. Normal conversion operating modes
  95. Injected channel conversion
  96. Abort conversion
  97. Analog clock generator and conversion timings
  98. Programmable analog watchdog
  99. DMA functionality
  100. External decode signals delay
  101. Register descriptions
  102. Control logic registers
  103. Main Status Register (MSR)
  104. Interrupt registers
  105. Channel Pending Registers (CEOCFR[1..2])
  106. Interrupt Mask Register (IMR)
  107. Channel Interrupt Mask Register (CIMR[1..2])
  108. Watchdog Threshold Interrupt Status Register (WTISR)
  109. Watchdog Threshold Interrupt Mask Register (WTIMR)
  110. DMA registers
  111. DMA Channel Select Register (DMAR[1..2])
  112. Threshold registers
  113. Threshold Register (THRHLR[0:3])
  114. Conversion timing registers CTR[1..2]
  115. Mask registers
  116. Injected Conversion Mask Registers (JCMR[1..2])
  117. Delay registers
  118. Data registers
  121. Reset Configuration Half Word Source (RCHW)
  122. Single-chip boot mode
  123. Boot and alternate boot
  124. BAM software flow
  125. BAM resources
  126. Download and execute the new code
  127. Download start address, VLE bit and code size
  128. Download data
  129. Boot from UART
  130. Bootstrap with CAN
  131. Protocol
  132. Interrupts
  134. Main features
  135. CAN Sampler Sample Registers 0–11
  137. Enabling/disabling the CAN Sampler
  138. Baud rate generation
  139. Clock architecture
  140. Auxiliary clocks
  141. Clock gating
  142. Clock Generation Module (MC_CGM)
  147. Output clock multiplexing
  148. FXOSC external oscillator
  150. KHz OSC digital interface
  152. SIRC digital interface
  157. Modulation Register (MR)
  159. Normal mode with frequency modulation
  160. Powerdown mode
  161. Clock Monitor Unit (CMU)
  163. Crystal clock monitor
  164. Memory map and register description
  165. Control Status Register (CMU_CSR)
  166. Frequency Display Register (CMU_FDR)
  167. Low Frequency Reference Register FMPLL0 (CMU_LFREFR)
  168. Measurement Duration Register (CMU_MDR)
  169. Device-specific information
  170. eMIOS clocking configuration
  171. Unified Channel block
  175. Unified Channel memory map
  177. eMIOS200 Global FLAG Register (EMIOSGFLAG)
  178. eMIOS200 Output Update Disable (EMIOSOUDIS)
  179. eMIOS200 Disable Channel (EMIOSUCDIS)
  180. eMIOS200 UC A Register (EMIOSA[n])
  181. eMIOS200 UC B Register (EMIOSB[n])
  182. eMIOS200 UC Counter Register (EMIOSCNT[n])
  183. eMIOS200 UC Status Register (EMIOSS[n])
  185. Unified Channel (UC)
  186. UC modes of operation
  187. Input Programmable Filter (IPF)
  188. Clock Prescaler (CP)
  189. Effect of Freeze on the Unified Channel
  190. Effect of Freeze on the GCP
  191. Coherent accesses
  194. General operation
  195. Slave ports
  199. Slave mode
  200. Signal names and descriptions
  203. DSPI Transfer Count Register (DSPIx_TCR)
  204. DSPI Status Register (DSPIx_SR)
  205. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
  206. DSPI POP RX FIFO Register (DSPIx_POPR)
  207. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
  211. Serial Peripheral Interface (SPI) configuration
  212. SPI Master mode
  213. Receive First In First Out (RX FIFO) buffering mechanism
  214. DSPI baud rate and clock delay generation
  215. Baud rate generator
  216. Transfer formats
  217. Classic SPI transfer format (CPHA = 0)
  218. Classic SPI transfer format (CPHA = 1)
  219. Modified SPI transfer format (MTFE = 1, CPHA = 0)
  220. Modified SPI transfer format (MTFE = 1, CPHA = 1)
  221. Continuous selection format
  222. Clock polarity switching between DSPI transfers
  223. Continuous serial communications clock
  224. Interrupts/DMA requests
  225. Transmit FIFO underflow interrupt request (TFUF)
  226. Module Disable mode
  227. Baud rate settings
  228. Delay settings
  233. Detailed signal descriptions
  234. Memory map and register definition
  235. Register summary
  237. Control Descriptor L0_2 Register
  238. Control Descriptor L0_3 Register
  239. Control Descriptor L0_4 Register
  240. Control Descriptor L0_5 Register
  241. Control Descriptor L0_6 Register
  242. Control Descriptor L0_7 Register
  243. Control Descriptor Cursor 2 Register (CtrlDescCursor_2)
  244. Control Descriptor Cursor 3 Register (CtrlDescCursor_3)
  245. DCU Mode Register (DCU_MODE)
  246. BGND Register
  247. DISP_SIZE Register
  248. HSYN_PARA Register
  249. SYN_POL Register
  250. Threshold Register
  251. Interrupt Status Register (INT_STATUS)
  252. Interrupt Mask Register (INT_MASK)
  253. COLBAR Registers
  254. Divide Ratio (DIV_RATIO) register
  255. SIGN_CALC_1 Register
  256. SIGN_CALC_2 Register
  257. PDI Status Register
  258. PDI Status Mask Register
  259. Parameter Error Status (PARR_ERR) register
  260. Mask PARR_ERR Status register
  261. THRESHOLD_INP_BUF_1 Register
  262. LUMA Component Register
  263. Red Chroma Components
  264. Blue Chroma Component Register
  265. CRC_POS Register
  266. FG0_bcolor
  267. Global Protection Register
  268. Soft Lock Bit Register L0
  269. Soft Lock Bit Register L1
  270. Soft Lock DISP_SIZE Register
  271. Soft Lock HSYNC/VSYNC PARA Register
  272. Soft Lock POL Register
  273. Soft Lock L1_TRANSP Register
  275. TFT LCD panel configuration
  276. DCU mode selection and background color
  277. Layer configuration and blending
  278. Control Descriptors
  279. Graphics and data format
  280. Alpha and Chroma-key blending
  281. 16 Freescale Semiconductor
  282. Transparency mode and blending
  283. Luminance mode
  284. Hardware cursor
  285. CLUT/Tile RAM
  286. Gamma correction
  287. Synchronizing to panel frame rate
  288. Error detection
  290. List of protected registers
  291. CRC area description
  293. Programming for Debug mode
  294. ITU-R BT.656 sync information extraction
  295. PDI interface description
  296. PDI interaction with other modules
  298. Modes of operation based on sync extraction
  299. Mode of operation depending on PDI_datain
  300. PDI-related interrupts
  301. Glossary
  306. DMA channels with no triggering capability
  307. Initialization/application information
  308. Enabling a source without periodic triggering
  309. Disabling a source
  311. Microarchitecture summary
  313. Integer unit features
  314. Unimplemented SPRs and Read-only SPRs
  315. Information specific to this device
  318. Memory map/register definition
  320. DMA Error Status (DMAES) register
  321. DMA Enable Request (DMAERQH, DMAERQL) registers
  322. DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) registers
  323. DMA Set Enable Request (DMASERQ) register
  324. DMA Clear Enable Request (DMACERQ) register
  325. DMA Clear Enable Error Interrupt (DMACEEI) register
  326. DMA Clear Interrupt Request (DMACINT) register
  327. DMA Set START Bit (DMASSRT) register
  328. DMA Interrupt Request (DMAINTH, DMAINTL) registers
  329. DMA Error (DMAERRH, DMAERRL) registers
  330. DMA Hardware Request Status (DMAHRSH, DMAHRSL) registers
  331. DMA General Purpose Output Register (DMAGPOR) register
  332. DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63} registers
  333. Transfer Control Descriptor (TCD)
  335. DMA basic data flow
  336. DMA performance
  338. DMA programming errors
  339. DMA arbitration mode considerations
  340. Fixed group arbitration, round-robin channel arbitration
  341. Multiple requests
  342. TCD status
  343. Preemption status
  344. Dynamic programming
  345. Hardware request release timing
  348. Processor Core Type (PCT) register
  349. Miscellaneous Wakeup Control Register (MWCR)
  350. Miscellaneous Interrupt Register (MIR)
  351. Miscellaneous User-Defined Control Register (MUDCR)
  352. ECC registers
  353. ECC Status Register (ESR)
  354. ECC Error Generation Register (EEGR)
  355. Flash ECC Address Register (FEAR)
  356. Flash ECC Master Number Register (FEMR)
  357. Flash ECC Data Register (FEDR)
  358. RAM ECC Address Register (REAR)
  359. RAM ECC Master Number Register (REMR)
  360. RAM ECC Data Register (REDR)
  361. High-priority enables
  365. Flash module sectorization
  366. User mode operation
  367. Reset
  368. Power-Down mode
  370. Module Configuration Register (MCR)
  371. Low/Mid Address Space Block Locking Register (LML)
  372. 17.2.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (NVLML
  373. High Address Space Block Locking Register (HBL)
  374. Secondary Low/Mid Address Space Block Locking Register (SLL)
  375. Low/Mid aDdress Space Block Select Register (LMS)
  376. High Address Space Block Select Register (HBS)
  377. Address Register (ADR)
  378. Bus Interface Unit 0 register (BIU0)
  379. Bus Interface Unit 2 register (BIU2)
  380. User Test 0 register (UT0)
  381. User Test 1 register (UT1)
  382. User Test 2 register (UT2)
  383. User Multiple Input Signature Register 1 (UMISR1)
  384. User Multiple Input Signature Register 2 (UMISR2)
  385. User Multiple Input Signature Register 4 (UMISR4)
  386. Non-volatile private censorship PassWord 0 register (NVPWD0)
  387. Non-Volatile Private Censorship Password 1 Register (NVPWD1)
  388. Non-Volatile System Censoring Information 1 register (NVSCI1)
  389. Non-Volatile User Options register (NVUSRO)
  390. Programming considerations
  391. Error Correction Code (ECC)
  400. 17.3.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (NVLML
  408. User Multiple Input Signature Register 0 (UMISR0)
  410. User Multiple Input Signature Register 3 (UMISR3)
  412. Double Word program
  413. Sector erase
  414. User Test mode
  416. EEPROM emulation
  417. Censored mode
  422. Access protections
  423. Read cycles—buffer hit
  424. Access pipelining
  425. Bank1 temporary holding registers
  426. Read-While-Write functionality
  427. Wait-State emulation
  428. Timing diagrams
  429. Initialization / application information
  430. Flash memory setting recommendations
  432. FlexCAN module features
  434. Signal descriptions
  435. Message Buffer structure
  436. Rx FIFO Structure
  438. Control Register (CTRL)
  439. Free Running Timer (TIMER)
  440. Rx Global Mask (RXGMASK)
  441. Rx 14 Mask (RX14MASK)
  442. Error and Status Register (ESR)
  443. Interrupt Mask Register High (IMRH)
  444. Interrupt Mask Register Low (IMRL)
  445. Interrupt Flag Register High (IFRH)
  446. Rx Individual Mask Registers (RXIMR0–RXIMR63)
  448. Transmit process
  449. Receive process
  450. Matching process
  451. Data coherence
  452. Message Buffer deactivation
  453. Rx FIFO
  454. CAN protocol related features
  455. Overload frames
  456. Arbitration and matching timing
  457. Modes of operation: details
  460. FlexCAN Addressing and RAM size configurations
  463. Bypass mode
  465. Instruction register
  466. Boundary Scan register
  467. TAP Controller state machine
  468. Selecting an IEEE 1149.1-2001 register
  469. BYPASS instruction
  470. IDCODE instruction
  471. e200z0 OnCE controller
  472. e200z0 OnCE controller register description
  478. START Signal
  479. Slave Address Transmission
  480. Repeated START Signal
  481. Handshaking
  483. Generation of stop
  484. Generation of repeated START
  485. DMA application information
  488. Software vector mode
  489. Stop mode
  490. INTC Module Configuration Register (INTC_MCR)
  491. INTC Interrupt Acknowledge Register (INTC_IACKR)
  492. INTC End-of-Interrupt Register (INTC_EOIR)
  494. Interrupt Request Sources
  495. Peripheral Interrupt Requests
  496. Last-In First-Out (LIFO)
  497. Handshaking with processor
  498. Hardware vector mode handshaking
  501. ISR, RTOS, and task hierarchy
  502. Order of execution
  503. Priority Ceiling Protocol
  504. Software configurable interrupt requests
  505. Scheduling an ISR on another processor
  506. Proper setting of interrupt request priority
  513. LCD Prescaler Control Register (LCDPCR)
  514. LCD Contrast Control Register (LCDCCR)
  515. LCD Frontplane Enable Register 0 (FPENR0)
  516. LCD Frontplane Enable Register 1 (FPENR1)
  517. LCDRAM (Location 0)
  518. LCDRAM (Location 1)
  519. LCDRAM (Location 2)
  520. LCDRAM (Location 3)
  521. LCDRAM (Location 4)
  522. LCDRAM (Location 5)
  523. LCDRAM (Location 6)
  524. LCDRAM (Location 7)
  525. LCDRAM (Location 8)
  526. LCDRAM (Location 9)
  527. LCDRAM (Location 10)
  528. LCDRAM (Location 11)
  529. LCDRAM (Location 12)
  530. LCDRAM (Location 13)
  531. LCDRAM (Location 14)
  532. LCDRAM (Location 15)
  533. LCD clock and frame frequency
  534. Contrast adjustment
  535. LCD RAM
  536. LCD bias and modes of operation
  537. Operation in power saving modes
  538. Boost at switching
  540. LCD waveform examples
  541. duty multiplexed with 1/2 Bias mode
  542. Duty multiplexed with 1/3 Bias mode
  544. Duty multiplexed with 1/3 Bias
  546. Initialization information
  548. Features common to LIN and UART
  549. Fractional baud rate generation
  550. Operating modes
  551. Low-power mode (Sleep)
  552. Memory map and registers description
  554. LIN control register 1 (LINCR1)
  555. LIN interrupt enable register (LINIER)
  556. LIN status register (LINSR)
  557. LIN error status register (LINESR)
  558. UART mode control register (UARTCR)
  559. UART mode status register (UARTSR)
  560. LIN timeout control status register (LINTCSR)
  561. LIN output compare register (LINOCR)
  562. LIN fractional baud rate register (LINFBRR)
  563. LIN integer baud rate register (LINIBRR)
  564. LIN checksum field register (LINCFR)
  565. Buffer identifier register (BIDR)
  566. Buffer data register LSB (BDRL)
  567. Identifier filter enable register (IFER)
  568. Identifier filter match index (IFMI)
  569. Identifier filter mode register (IFMR)
  570. Identifier filter control register (IFCR2n)
  571. Identifier filter control register (IFCR2n + 1)
  572. Register map and reset values
  573. UART mode
  574. UART transmitter
  577. Slave mode with identifier filtering
  578. Slave mode with automatic resynchronization
  580. Output compare mode
  585. MPU Error Address Register, Slave Port n (MPU_EARn)
  586. MPU Error Detail Register, Slave Port n (MPU_EDRn)
  587. MPU Region Descriptor n (MPU_RGDn)
  588. 24.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn
  590. Access evaluation—hit determination
  591. Putting It All Together and AHB Error Terminations
  598. Mode Control Register (ME_MCTL)
  599. Mode Enable Register (ME_ME)
  600. Interrupt Status Register (ME_IS)
  601. Interrupt Mask Register (ME_IM)
  602. Invalid Mode Transition Status Register (ME_IMTS)
  603. Debug Mode Transition Status Register (ME_DMTS)
  604. Reset Mode Configuration Register (ME_RESET_MC)
  605. Test Mode Configuration Register (ME_TEST_MC)
  606. DRUN Mode Configuration Register (ME_DRUN_MC)
  607. Run0...3 Mode Configuration Registers (ME_RUN0...3_MC)
  608. Stop Mode Configuration Register (ME_STOP_MC)
  609. Peripheral Status Register 0 (ME_PS0)
  610. Peripheral Status Register 1 (ME_PS1)
  611. Peripheral Status Register 2 (ME_PS2)
  612. Run Peripheral Configuration Registers (ME_RUN_PC0...7)
  613. Low-Power Peripheral Configuration Registers (ME_LP_PC0...7)
  614. Peripheral Control Registers (ME_PCTL0...143)
  615. Mode details
  616. Test mode
  617. Run0...3 modes
  619. Standby mode
  620. Target mode request
  621. Peripheral Clocks Disable
  622. Processor Low-Power mode entry
  623. Flash Modules Switch-On
  624. Peripheral Clocks Enable
  625. Power Domain #2 Switch-Off
  626. FMPLL0 Switch-Off
  627. Current mode update
  628. Protection of mode configuration registers
  629. Safe mode transition interrupt
  630. Application Example
  634. Operating mode
  636. Port Configuration Register (PCR)
  637. Development Control Register 1, 2 (DC1, DC2)
  638. Development Status Register (DS)
  639. Read/Write Access Control/Status (RWCS)
  640. Read/Write Access Address (RWA)
  641. Watchpoint Trigger Register (WT)
  643. Enabling Nexus clients for TAP access
  644. Configuring the NDI for Nexus messaging
  645. Nexus messaging
  647. Signal description
  649. Current Timer Value (CVAL) register
  650. Timer Control (TCTRL) register
  652. Debug mode
  654. Read Cycles
  659. Power Domain #1 Configuration Register (PCU_PCONF1)
  660. Power Domain Status Register (PCU_PSTAT)
  661. Mode transitions
  662. Standby mode transition
  663. Power saving for memories during Standby mode
  664. Preface
  665. Glossary for QuadSPI module
  668. QuadSPI modes of operation
  669. Debug mode (SPI modes only)
  670. Detailed Signal Description
  671. QSPI_IO2—QuadSPI Data IO_2
  672. AMBA bus register memory map
  673. IP bus register descriptions
  674. Transfer Count Register (QSPI_TCR)
  675. SPI Status Register (QSPI_SPISR)
  676. PUSH TX FIFO Register (QSPI_PUSHR)
  677. POP RX FIFO Register (QSPI_POPR)
  678. Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)
  679. RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)
  680. Instruction Code Register (QSPI_ICR)
  681. Sampling Register (QSPI_SMPR)
  682. RX Buffer Status Register (QSPI_RBSR)
  683. RX Buffer Data Registers 0–14 (QSPI_RBDR0–QSPI_RBDR14)
  684. TX Buffer Status Register (QSPI_TBSR)
  685. TX Buffer Data Register (QSPI_TBDR)
  686. Serial Flash Mode Status Register (QSPI_SFMSR)
  687. Serial Flash Mode Flag Register (QSPI_SFMFR)
  688. AHB bus register memory map descriptions
  689. AHB bus access considerations
  691. SPI (Serial Peripheral Interface) modes
  692. Start and Stop of SPI Transfers
  693. Master mode
  695. Baud Rate and Clock Delay Generation
  696. SPI Transfer Formats
  698. SPI mode interrupt and DMA requests
  699. SFM (Serial Flash) mode
  700. Issuing SFM Commands
  701. Flash Programming
  702. Byte Ordering of Serial Flash Data
  703. Serial Flash mode interrupt and DMA requests
  704. TX Buffer Operation
  705. Power saving features
  706. Leaving power-saving modes
  707. Baud rate settings—SPI modes only
  708. Delay settings—SPI modes only
  709. Oak family compatibility with the QuadSPI—SPI modes only
  710. Calculation of FIFO pointer addresses—SPI modes only
  711. 30.6.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO
  712. Available status/flag information—SFM mode only
  713. Overview of error flags
  714. DMA usage
  715. Serial Flash Devices
  716. Supported Instruction Codes in Winbond Devices
  717. Serial Flash Clock Frequency Limitations
  723. Functional Event Status Register (RGM_FES)
  724. Destructive Event Status Register (RGM_DES)
  725. Functional Event Reset Disable Register (RGM_FERD)
  726. Destructive Event Reset Disable Register (RGM_DERD)
  727. Functional Event Alternate Request Register (RGM_FEAR)
  728. Destructive Event Alternate Request Register (RGM_DEAR)
  729. Functional Event Short Sequence Register (RGM_FESS)
  730. Standby Reset Sequence Register (RGM_STDBY)
  732. Phase0 Phase
  733. Phase1 Phase
  734. Destructive Resets
  735. Functional Resets
  736. Alternate Event Generation
  738. Device specific information
  739. Debug support
  740. RTC Control Register (RTCC)
  741. RTC Status Register (RTCS)
  742. RTC Counter Register (RTCCNT)
  743. API functional description
  745. Register memory map
  746. Reset effects on SRAM accesses
  747. Initialization and application information
  751. SOUND_DURATION register
  752. SGL_STATUS register
  755. PWM alignment modes
  758. M1C0M/M1C0P/M1C1M/M1C1P — PWM output pins for Motor 1
  760. Motor Controller Control Register 0 (MCCTL0)
  761. Motor Controller Control Register 1 (MCCTL1)
  762. Motor Controller Period Register (MCPER)
  763. Motor Controller Duty Cycle Register (MCDC0..11)
  764. Short-circuit Detector Timeout Register (MCSDTO)
  765. Short-circuit Detector Enable Register 1 (MCSDE1)
  766. Short-circuit Detector Interrupt Enable Register 0 (MCSDIEN0)
  767. Short-circuit Detector Interrupt Enable Register 2 (MCSDIEN2)
  768. Short-circuit Detector Interrupt Register 1 (MCSDI1)
  769. and PWM mode functions
  770. PWM Duty Cycle
  771. Output switching delay
  777. Interrupt Enable and Flag Register (IRQ)
  778. Integration Accumulator Register (ITGACC)
  779. Blanking Counter Load Register (BLNCNTLD)
  780. SSD Prescale and Divider Register (PRESCALE)
  782. Analog Wrapper + Port Control
  783. Register Interface
  784. BIS control
  785. Stepper Stall Detection Measurement
  786. Details of the SSD Measurement
  787. Additional modes of operation
  788. SSD startup
  789. Setting of the PRESCALE Register
  790. Offset Cancellation Considerations
  791. Stepper Motor Transition Considerations
  792. Legacy modes—separate blanking and integration phase
  797. MCU ID Register #2 (MIDR2)
  798. Interrupt Status Flag Register (ISR)
  799. Interrupt Rising-Edge Event Enable Register (IREER)
  800. Interrupt Filter Enable Register (IFER)
  801. GPIO Pad Data Output Registers (GPDO0_3–GPDO132_135)
  802. Parallel GPIO Pad Data Out Registers (PGPDO0–PGPDO4)
  803. Parallel GPIO Pad Data In Register (PGPDI0–PGPDI4)
  804. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
  806. External interrupts
  807. External interrupt management
  810. System Status Register (STATUS)
  811. Error Configuration
  812. Debug Status Port Register
  813. Password Comparison Registers
  818. STM Count Register (STM_CNT)
  819. STM Channel Control Register (STM_CCRn)
  820. STM Channel Compare Register (STM_CMPn)
  825. VREG digital interface
  826. GPIO power supply configuration
  827. Power domain organization
  832. NMI Configuration Register (NCR)
  833. Wakeup/Interrupt Status Flag Register (WISR)
  834. Interrupt Request Enable Register (IRER)
  835. Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)
  836. Wakeup/Interrupt Pullup Enable Register (WIPUER)
  837. NMI Management
  838. External Wakeups/Interrupts
  840. On-Chip Wakeups
  841. Appendix A
  842. Registers Under Protection
  847. Appendix B
  848. Register Map
  913. C.1 Changes between revisions 6 and 7
  914. C.2 Changes between revisions 5 and 6
  915. C.3 Changes between revisions 4 and 5
  916. C.4 Changes between revisions 3 and 4
  917. C.5 Changes between revisions 2 and 3
  918. C.6 Changes between revisions 1 and 2
  919. C.7 Changes between revisions 0 and 1
NXP Semiconductors MPC5606S Reference Manual Manual pdf 1 page image
MPC5606S Microcontroller Reference Manual, Rev. 7Freescale SemiconductorMPC5606S Microcontroller ReferenceManualSupports MPC5602S, MPC5604S and MPC5606S
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This manual is suitable for:
MPC5602SMPC5604SMPC5606S
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