Hardware User Guide4-6 Xilinx Development SystemSeries™ software. Use these tutorial designs to learn the ISP designflow.Schematic With VHDL Macro DesignJCT_SVHD is a simple 8-bit Johnson counterDESIGN FLOW: Schematic (JCT_SVH1.SCH) with XVHDLmacro (JCOUNTER.VHD)TARGET DEVICE: XC9536-VQ44 (any speed)I/O Pins:CLK : input free-running clockQ0-Q7 : counter outputsOPERATION:The counter is triggered on rising edge of theclock(CLK).The following is the sequence of states on outputsQ Q7-Q0:0000000000000001000000110000011100001111000111110011111101111111111111101111111011111100111110001111000011100000110000001000000000000000 (repeats)SIMULATION WAVEFORMS:
