FPGA Design Demonstration BoardHardware User Guide 3-21To configure from the onboard serial PROM, these switches must beoff. This places the FPGA in master serial mode.MCLK-Master Clock (SW1-7)When this switch is on, it connects the XC4003E configuration clock(pin 73) to the configuration clock on the XC3020A (pin 60). Thisconnection is used to configure FPGAs in a daisy chain with theXC4003E at the head.DOUT-Data Out (SW1–8)When this switch is on, it connects the XC4003E data out line (pin 72)to the data in line of the XC3020A. This connection configures FPGAsin a daisy chain with the XC4003E at the head.Note MCLK and DOUT should only be used to configure the FPGAsin a daisy chain.XChecker/Parallel Cable III Connector J1The following table describes the pins and functions of theXChecker/Parallel Cable III J1 connector.Table 3-7 XChecker/Parallel Cable III Connector J1Pin Name Function Pin Name FunctionJ1–1a VCC Supplies +5 V to theXChecker Cable.J1–2 RT Allows XCheckerCable to trigger a read-back of the XC3020A.Connects to XC3020Apin 26.J1–3a GND Supplies groundreference toXChecker Cable.J1–4 RD Used by XCheckerCable for readbackdata. Connects toXC3020A pin 25.
