FPGA Design Demonstration BoardHardware User Guide 3-17The D/P wire from the FPGA header on the Parallel Cable III isconnected to J2-9 DONE pin.Jumper J7 and Tiepoints J10 (1-3)Jumper J7 allows the XChecker signal RST on J2-17 to drive the resetline on the demonstration board. Tiepoint pins jumper the followingXChecker signals into the circuit. Tiepoint J10-1 connects to TRIG onJ2-6; Tiepoint J10-2 connects to CLK1 on J2-16; and, Tiepoint J10-3connects to CLK0 on J2-18. See the preceding table for more details onthe cable and pin connections.Serial PROM Socket (U2)This serial PROM configures the XC4003E or the XC4003E andXC3020A connected in a daisy chain. The configuration mode mustbe in the master serial mode to configure from the serial PROM.J2-15 INIT Goes Low if CRCerror occurs duringconfiguration.Connects toXC4003E INIT pin41.J2-16 CLK1 A system clock input toXChecker Cable to becontrolled and output onCLK0.Connects to tiepoint J10-2.J2-17 RST Connects to jumperJ7. If connected,allows XCheckerCable to provide aReset input (same aspressing the Resetbutton).J2-18 CLK0 A system clock outputcontrolled by XCheckerCable. Used to single-step or burst clocks tothe XC4003E.Connects to tiepoint J10-3.a. Denotes pins supported by the Parallel Cable IIIb. No pin connectionTable 3-6 XChecker/Parallel Cable III Connector J2Pin Name Function Pin Name Function
