Hardware User Guide2-18 Xilinx Development SystemFigure 2-10 SelectMAP Mode (Virtex with AsynchronousProbing)JTAG Mode (XC9000, Virtex, Spartan, XC5200,XC4000)The following figure shows in detail the JTAG Mode connections forXC9000, Virtex, Spartan, XC5200, and XC4000 devices.D0D1D2D3D4D5D6D7RDY/BUSYCS2CS1CS0 (CS)WSGNDCCLKDINRTTDITCKTMSRSTTRIGRD (TDO) PWRVccoRS (RDWR)CLK2-INCLK2-OUTCLK1-INCLK1-OUTDONE (D / P)PROGINIT4231NOTE: Pull-up resistors are 4.7k ohm.Circuit BoardXILINX deviceMultiLINX ConnectorsVCCVCC VccoVcco(optional)System Clock (x)System Clock (y)(optional)M0M1M2CCLKCSDONEPROGRAMINITD7D6D5D3D4D2D1D0WRITEBUSY/DOUTGCK (x)GCK (y)User Logicflip-flops & latches,LUTRAMS,& block RAMSCapture ControlLogicCAPTURECAPCLKUser I/O: RESETUser I/O: TRIGGERUser I/O(optional)X8935
