Hardware User Guide1-20 Xilinx Development SystemThe following figures show which pins to connect, depending onyour chosen FPGA device. For descriptions of each pin, see Table 3-6and Table 3-7 of the “FPGA Design Demonstration Board” chapter.Use Header 1 (see Figure 1-9) to connect the XChecker Cable to thetarget system for configuring FPGAs. When configuring XC4000FPGAs, the RST (Reset) wire is not used as shown in the followingfigure.Figure 1-11 XChecker Connections to XC4000 DeviceTo configure XC3000 FPGAs, the PROG wire is not used. This isshown in the following figure. In both cases, the FPGA must be in theSerial Slave Mode.Figure 1-12 XChecker Connections to XC3000 DevicePin Connection ConsiderationsThe following adjustments will make the process of connecting anddownloading easier.XChecker with Header 1 Target SystemX8323CCLKGNDVCCINITRSTDONEDINPROGINITXC4000 FPGA in Slave Serial ModeNot UsedVCCGNDPROGCCLKD/PDINXChecker with Header 1 Target SystemX8324CCLKGNDVCCINITPROGD/PDININITXC3000 FPGA in Slave Serial ModeNot UsedRESETVCCGNDRSTCCLKD/PDIN
