FPGA Design Demonstration BoardHardware User Guide 3-9Seven-Segment Displays (U6, U7, U8)Three seven-segment displays are included with the leftmost display(U6) connect to the XC3020A FPGA. The rightmost two displays (U7and U8) connect to the XC4003E device.Each LED segment is turned on by driving the corresponding FPGApin ‘LOW’ with a logic ‘0.’ The decimal point on U8 connects to theINIT pin of the XC4003E (pin 41) and serves as a programming errorindicator. The decimal point should be on while the FPGA is in itsinternal clearing state, then it should remain off during configuration.If the decimal point comes back on, a programming error hasoccurred.The decimal points on U6 and U7 are tied to the Low During Config-uration (LDC) pins of the XC3020A and XC4003E, respectively. Thedecimal points are on while the FPGAs wait to be configured.The following table shows the I/O pin definitions. The followingfigure shows the seven-segment display of the FPGA demonstrationboard.Table 3-3 Seven-Segment I/O ConnectionsDisplay Segment XC3020A XC4003E XC4003EU6 U7 U8a 38 39 49b 39 38 48c 40 36 47d 56 35 46e 49 29 45f 53 40 50g 55 44 51decimal point 30 37 41
