FPGA Design Demonstration BoardHardware User Guide 3-25N = approximately 0.35 for TTl threshold= approximately 0.75 for CMOS thresholdwhen the FPGA allows each capacitor to discharge during the oppo-site timing phase.Mode Switch SettingsThis section describes the SW1 and SW2 switch settings for config-uring the XC3020A and XC4003E devices.• From the XChecker/Parallel Cable III• From the serial PROM (single program)• From the serial PROM (multiple program)• In a daisy chainThe following table lists the names and positions of the SW1 and SW2switches for configuring the XC3020A FPGA from the XChecker orParallel Cable III.Table 3-8 Configuring the XC3020A from the XChecker/ParallelCable IIISwitch Name Position Switch Name PositionSW1–1 INP X SW2–1 PWR XSW1–2 MPE OFF SW2–2 MPE XSW1–3 SPE OFF SW2–3 SPE XSW1–4 M0 ON SW2–4 M0 XSW1–5 M1 ON SW2–5 M1 XSW1–6 M2 ON SW2–6 M2 XSW1–7 MCLK OFF SW2–7 RSTSW1–8 DOUT OFF SW2–8 INIT OFFX indicates don‘t care
