Xilinx Virtex-6 FPGA User Manual

Also see for Virtex-6 FPGA: User guide User guide Guide Hardware setup guide User guide

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Xilinx Virtex-6 FPGA User Manual Manual pdf 112 page image

112 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideUG371 (v2.0) February 16, 2010Chapter 4: ReceiverRX Pattern CheckerFunctional DescriptionThe GTH receiver contains a built-in pattern checker block. The checker supports thefollowing PRBS patterns:• PRBS7• PRBS9• PRBS11• PRBS23• PRBS31In 64B/66B mode (for example, when the GTH transceiver is configured with the10GBASE-R protocol), the checker is forced into PRBS31 mode when PRBS31 test patternmode is enabled.The PRBS checker module implements a 32-bit error counter and a 48-bit timer. The errorcounter and timer function as follows:• The first read of any error counter/timer register latches both the error counter/timerin shadow flops.• If the read was of an error counter and clear-on-read is on, both the timer and errorcounter are cleared.• Reads of just the timer register (i.e., without first reading the error counter) do notclear the error count/timer, even if clear-on-read mode is on.• Subsequent reads from error counter/timer addresses greater than the previous readaddress only read the shadow flops, do not read the actual state of the errorcounter/timer, and do not clear the error counter timer.• Subsequent reads from error counter/timer addresses equal to or less than the read ofthe previous error counter/timer start the process over.The error and sample counters saturate when they reach the maximum value.In pattern check mode, data does not appear on RXDATA ports.