66 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideUG371 (v2.0) February 16, 2010Chapter 2: Shared Transceiver FeaturesFollow these steps to reset the receive datapath in the GTH transceiver:1. Change RXPOWERDOWN[1:0] to 2'b10 and wait for RXCTRLACK to goHigh. The CDR is disabled.2. Change RXPOWERDOWN[1:0] to 2'b00 and wait for RXCTRLACK to goHigh. The CDR is enabled.3. Assert RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready fornormal operation.Power DownFunctional DescriptionThe GTH transceiver offers different levels of power control. Part of the power-downfunctionality includes resetting certain logic within the GTH transceiver.Ports and AttributesTable 2-12 defines the power-down ports.Table 2-12: Power-Down PortsPort Dir Clock Domain DescriptionPOWERDOWN0POWERDOWN1POWERDOWN2POWERDOWN3In TXUSERCLKIN0TXUSERCLKIN1TXUSERCLKIN2TXUSERCLKIN3This control signal powers off the corresponding lane. It isused to place individual lanes in a low power state. Thisport is used on a per-lane basis even when multiple lanesare configured as a single logical link.RXPOWERDOWN0[1:0]RXPOWERDOWN1[1:0]RXPOWERDOWN2[1:0]RXPOWERDOWN3[1:0]In TXUSERCLKIN0TXUSERCLKIN1TXUSERCLKIN2TXUSERCLKIN3This control signal requests the receiver power state:00: Normal operation10: Power-off receiver logic. The PLL continues tooperate in this state.This port must always be set to 2'b10 during initializationand when GTHRESET is asserted.If the Quad is configured as a x4 link, only the port fromLane 0 is valid.TXPOWERDOWN0[1:0]TXPOWERDOWN1[1:0]TXPOWERDOWN2[1:0]TXPOWERDOWN3[1:0]In TXUSERCLKIN0TXUSERCLKIN1TXUSERCLKIN2TXUSERCLKIN3This control signal requests the transmitter power state:00: Normal operation10: Power-off transmitter logic. The PLL continues tooperate in this state.This port must always be set to 2'b10 during initializationand when GTHRESET is asserted.If the Quad is configured as a x4 link, only the port fromLane 0 is valid.
