Xilinx Virtex-6 FPGA User Manual

Also see for Virtex-6 FPGA: User guide User guide Guide Hardware setup guide User guide

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Xilinx Virtex-6 FPGA User Manual Manual pdf 69 page image

Virtex-6 FPGA GTH Transceivers User Guide www.xilinx.com 69UG371 (v2.0) February 16, 2010LoopbackPorts and AttributesThere are no loopback ports.Table 2-14 defines the loopback attributes..Table 2-14: Loopback AttributesAttribute Type DescriptionPMA_LPBK_CTRL_LANE0PMA_LPBK_CTRL_LANE1PMA_LPBK_CTRL_LANE2PMA_LPBK_CTRL_LANE316-bit Hex This attribute configures the PMA loopback mode.[15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA GTHTransceiver Wizard.[1:0]: Configure the source of the on-chip loopback connection to the RX:2’b00: User loopback disabled2’b01: TX output2’b10: TX pre-driver2’b11: ReservedPCS_MODE_LANE0PCS_MODE_LANE1PCS_MODE_LANE2PCS_MODE_LANE316-bit Hex This attribute sets the PCS mode.[15]: Loopback serializer/deserializer RX to serializer/deserializer TX[14]: Loopback PCS TX to PCS RX[13:11]: PRBS generator mode000: None001: PRBS7010: PRBS9011: PRBS11100: PRBS23101: PRBS31Others: Reserved[10:8]: PRBS checker mode000: None001: PRBS7010: PRBS9011: PRBS11100: PRBS23101: PRBS31Others: Reserved[7:4]: PCS RX mode0000: Zero0001: 64B/66B0111: 8B/10B1010: 16-bit raw data1011: 20-bit raw data1100: PRBSOthers: Reserved[3:0]: PCS TX mode0000: Zero0001: 64B/66B0111: 8B/10B1010: 16-bit raw data1011: 20-bit raw data1100: PRBSOthers: Reserved