62 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideUG371 (v2.0) February 16, 2010Chapter 2: Shared Transceiver Features12. Change RXRATE[1:0] to the value used for the application and wait forRXCTRLACK to go High.13. Change RXPOWERDOWN[1:0] to 2'b00.14. Wait for RXCTRLACK to go High.15. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready fornormal operation.Note relevant to Figure 2-7:1. The TXCTRLACK and RXCTRLACK signals can be High for more than1 DCLK clock cycle.GTH Quad Reset in Response to GTHRESETGTHRESET is used as a reset to all four GTH lanes within the Quad, including the PLL.Besides resetting the GTH Quad, GTHRESET also changes the Quad to its defaultconfiguration of 10GBASE-R. If the GTH Quad has a different configuration from thedefault of 10GBASE-R, the design must also assert GTHINIT after GTHRESET isdeasserted.Figure 2-8 shows the reset sequence of the GTH Quad following the assertion ofGTHRESET when the GTH transceiver is configured in full line rate mode (i.e., theTXRATE[1:0], SAMPLERATE[2:0], and RXRATE[1:0] ports are set to all zeros).Follow these steps to reset the GTH transceiver, when configured in full line rate mode:1. Set PCS_MODE_LANE[7:4] and PCS_MODE_LANE[3:0] to the datapathmode used in the application for RX and TX, respectively.2. Set PCS_RESET_LANE to the datapath mode used in the application.3. Set PCS_RESET_1_LANE to the datapath mode used in the application.4. Set TXPOWERDOWN[1:0] and RXPOWERDOWN[1:0] to 2'b10.5. Assert GTHRESET for 1 DCLK clock cycle. The TXCTRLACK andRXCTRLACK ports from all four lanes are asserted.X-Ref Target - Figure 2-7Figure 2-7: GTH Transceiver Initialization when in Divided Line Rate ModeGTHINITDONEGSRTXRATE [1:0]SAMPLERATE[2:0]TXPOWERDOWN[1:0]TXBUFRESETTXCTRLACKRXCTRLACKRXRATE[1:0]RXPOWERDOWN[1:0]RXBUFRESETUG371_c2_04_0826092’b00 USER_TXRATE3’b000 USER_SAMPLERATE2’b10 2’b002’b00 USER_RXRATE2’b10 2’b00
