Xilinx Virtex-6 FPGA User Manual
Also see for Virtex-6 FPGA: User guideUser guideGuideHardware setup guideUser guide
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Virtex-6 FPGA GTH Transceivers User Guide www.xilinx.com 117UG371 (v2.0) February 16, 2010RX Raw Mode• Management Interface Address:The Lane Address setting is used to specify which GTH lane to access:• PRBS_ERR_CNT0: 0x8002 with MMD Address 0x03• PRBS_ERR_CNT1: 0x8003 with MMD Address 0x03• PRBS_TIMER_0: 0x8004 with MMD Address 0x03• PRBS_TIMER_1: 0x8005 with MMD Address 0x03• PRBS_TIMER_2: 0x8006 with MMD Address 0x03RX Raw ModeFunctional DescriptionThe GTH transceiver provides another datapath mode for non-encoded applications orwhen the user wants to bypass the 8B/10B and 64B/66B blocks.Ports and AttributesTable 4-12 defines the RX raw mode ports..Table 4-12: RX Raw Mode PortsPort Dir Clock Domain DescriptionRXCODEERR0[7:0]RXCODEERR1[7:0]RXCODEERR2[7:0]RXCODEERR3[7:0]Out RXUSERCLKIN0RXUSERCLKIN1RXUSERCLKIN2RXUSERCLKIN3These outputs indicate an error occurred on RXDATA |
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