Xilinx Virtex-6 FPGA User Manual

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Xilinx Virtex-6 FPGA User Manual Manual pdf 56 page image

56 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideUG371 (v2.0) February 16, 2010Chapter 2: Shared Transceiver Features• Asserting GTHRESET not only resets the GTH Quad but also changes itsconfiguration back to its default of 10GBASE-R. For example, if the design isconfigured for OC-192, asserting GTHRESET changes the configuration to10GBASE-R.• To keep the user configuration after GTHRESET is deasserted, GTHINIT must bepulsed.• Both TXUSERCLKIN and RXUSERCLKIN clocks must be stable whenTXPOWERDOWN and RXPOWERDOWN are set in normal operation mode.• The PCS_MODE_LANE, PCS_RESET_LANE, and PCS_RESET_1_LANEattributes must be set to the datapath mode configuration used in the application.Ports and AttributesTable 2-10 defines the reset ports.Table 2-10: Reset PortsPort Dir Clock Domain DescriptionDCLK In N/A This input is the DRP interface clock. It is also used as themanagement interface clock when the managementinterface is enabled. This clock must be connected andavailable all the time for the GTHE1_QUAD primitive toinitialize properly, even if the DRP or the managementinterface is not used in the design.GTHINIT In DCLK This input triggers the programming of the attributessetting from configuration memory to the registers in theGTHE1_QUAD primitive.This port must be asserted for 1 DCLK clock cycle.GTHINITDONE Out DCLK This port is driven High upon completion of programmingthe bits from the configuration memory to the registers inthe GTHE1_QUAD primitive.This output is driven Low when GTHRESET or GTHINIT isasserted. It remains Low until after the assertion ofGTHINIT.GTHRESET In DCLK This port resets the GTHE1_QUAD primitive. When thisport is asserted, the configuration of all GTH transceiverswithin the GTHE1_QUAD primitive reverts to the defaultsetting of 10GBASE-R. To maintain the same userconfiguration, GTHINIT must be pulsed after GTHRESETis deasserted.This port must be asserted for 1 DCLK clock cycle.RXBUFRESET0RXBUFRESET1RXBUFRESET2RXBUFRESET3In RXUSERCLKIN0RXUSERCLKIN1RXUSERCLKIN2RXUSERCLKIN3This input resets the buffer inside the RX data converter (seeFigure 4-5, page 136). Both the internal RX clock andRXUSERCLKIN (1) must be stable before a reset can beapplied to the buffer.