Xilinx Virtex-6 FPGA User Manual

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Xilinx Virtex-6 FPGA User Manual Manual pdf 72 page image

72 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideUG371 (v2.0) February 16, 2010Chapter 2: Shared Transceiver FeaturesUsing the Management InterfaceFollow these steps to enable the management interface:1. Drive the DISABLEDRP port Low during GTH transceiver initialization.2. When the GTHINITDONE signal goes High from completion of GTH transceiverinitialization, drive the DISABLEDRP port High.One example for implementing the above sequence in logic is to tie the DISABLEDRP portto the inverter of GTHINITDONE.Note: When the setting on the DISABLEDRP port is changed to switch between the DRP interfaceand the management interface, the user must wait two DCLK cycles for the change to take effectbefore accessing the registers.Figure 2-15 is a timing diagram for reading the register through the management interface.The read access consists of MMD, GTH lane select, register address signals, and a singlecycle pulse of the MGMTPCSREGRD signal. The read addresses must be held until theread access completes and returns an acknowledgment through the MGMTPCSRDACKsignal. A read operation can be requested right after the acknowledgment indicator signalas shown in Event 1 of Figure 2-15. No read or write operation can be requested prior to theacknowledgment indicator signal.X-Ref Target - Figure 2-15Figure 2-15: Management Interface Read Access Timing DiagramDISABLEDRPDCLKMGMTPCSLANESEL[3:0]MGMTPCSMMDADDR[4:0]MGMTPCSREGADDR[15:0]MGMTPCSREGWRMGMTPCSWRDATA[15:0]MGMTPCSREGRDMGMTPCSRDACKMGMTPCSRDDATA[15:0]UG371_c2_12_020810(Select GTH Lane)(Select MMD Address)(Select Management Register Address)16’h0000(Event 1)16’h0000